Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

Narasimham, B.; Bhuva, B. L.; Schrimpf, R.D.; Massengill, L.W.; Gadlage, Matthew J.; Amusan, O.A.; Holman, W.T.; Witulski, A.F.; Robinson, William H.; Black, Jeffrey D.; Benedetto, J.M.; Eaton, P.H.

doi:10.1109/tns.2007.910125

Cited by 158 publications

(76 citation statements)

References 12 publications

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“…For a balanced gate V0 ~ ½ ܸ݀݀. Parameter ݇[ܸ ିଵ ] is a measure of the function slope at ܸ݅݊ = ‫ܸ‬ results in a large change of ‫ݐݑܸ‬ toward ܸ݀݀ or ‫.ܦܰܩ‬The values of both ܸ0 and ݇ parameters are obtained by fitting the simulated data to (1).These parameters also contain the dependence of the function with the gate fan-out, as they depend on the gate delay. Dependence of ‫ݐݑܸ‬ with the pulse width is described through parameters ܸ0.and ݇.…”

Section: Gate-level Soft Error Propagation Modelmentioning

confidence: 99%

“…This is caused by the strike of an ionizing particle that deposits an amount of charge at the node parasitic capacitance [1]. Such perturbation can propagate within the combinational block and eventually reach a memory element that might erroneously change its stored value because of soft error.Soft error is extensively studied and propagation within given circuits are understood.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Mitigation of Soft Errors on 65NM Combinational Logic Gates via Buffer Gate

Hosseini¹,

Jahanirad²

2015

VLSICS

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Section: Gate-level Soft Error Propagation Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mitigation of Soft Errors on 65NM Combinational Logic Gates via Buffer Gate

Hosseini¹,

Jahanirad²

2015

VLSICS

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show abstract

“…As technology feature size shrinks, increased frequency and reduced supply voltage result in more transient faults being propagated to latches or primary outputs of circuits and creates more failures than before [2,3]. Therefore, reliability evaluation approaches and soft error rate (SER) analysis of logic circuits are needed to meet the increasing demand on reliable design [4,5].…”

Section: Introductionmentioning

confidence: 99%

Reliability evaluation of logic circuits based on transient faults propagation metrics

Cai

Wang

et al. 2017

IEICE Electron. Express

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Reliability has been an important consideration in designing modern circuits due to the nanometric scaling of CMOS technology. This paper proposes a reliability evaluation approach for logic circuits based on transient faults propagation metrics (TFPMs). In this approach, TFPMs of each nodes are calculated through reverse topological traversal of the target circuit by Boolean operations in parallel. Using these faults propagation features, the reliability of combinational circuits and full scan sequential circuits are evaluated efficiently. Experimental results and statistic analysis show the proposed approach can achieve about three orders of magnitude faster than Monte Carlo simulation (MCS) while maintaining accuracy.

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“…In recent VLSI, such error pulses with wide width sometimes occur due to several reasons such as powersupply noise as analyzed in [19] and experimentally shown in [20], and thus they are not negligible. Therefore, it is necessary to detect or correct such error pulses occurring in a system.…”

Section: Introductionmentioning

confidence: 99%