Characterization of drop impact survivability of a 3D CSP stack module

Abstract

Chip scale packages (CSPs) are widely used in miniaturized electronic systems, and the performance advantages and reliability of single layer packages have been well studied for consumer applications. Three dimensional stacked modules allow for further miniaturization while retaining manufacturability and performance advantages, but they are not yet as widely used or investigated as single layer packages. Of particular concern is the survivability of a board mounted, stacked module under board level drop impact and shock loading, which may soon be of great importance in consumer, industrial and military applications. A CSP stack module is fabricated by stacking several CSPs to achieve high-density 3D systems without increasing the package's footprint. But it also introduces more probabilities of mechanical failure including drop impact-induced malfunction in solder interconnections. In order to evaluate the survivability of a stacked package, we have developed a model for a two level CSP stack module attached to a FR-4 board following the JEDEC standard. With this assembly undergoing drop impact in the 0º orientation (horizontal drop) under two types of impulse loads, we discuss the results of board-level impacts theoretically and numerically. Our results suggest that (1) the solder balls at the first CSP level are the determining factor in package reliability, (2) the first CSP level is most susceptible to damage and failure for the horizontal drop, and (3) damages in the higher level solder joints are due to a combination of vibration induced and stress wave induced stresses.

Failure Mechanism of stacked CSP module under board-level drop impact

“…The comparison of the 2 figures implies that a larger k (i.e., the solders act stiffer) results in a smaller solder stress oscillating at a higher frequency. Intriguingly, either from the numerical results in Figure 4 or from our previous calculations [2,9], we verified that the stresses in solders under a 0° drop could be so high as to reach one order of magnitude larger than that in the 90° drop, but oscillates at a much lower frequency. This comparison also indicates that the system acts more compliantly in the 0° drop than in the 90° drop, the same as was observed in the stress-wave propagation stage (but different in the underlying physics).…”

“…The dynamics of an S-CSP module under JEDECcompatible board-level drop testing has been characterized in [2] by showing that the corner-most joints at the bottom (ballout) level of the package are the most vulnerable to drop impact. The results also showed that those critical solder joints are likely to experience plastic yield as early as in the first tens of microseconds after impact inception, during which the impact-induced stress-wave propagation dominates the dynamics of the board-mount stacked-CSP assembly.…”