Characterization of Dynamic SRAM Stability in 45 nm CMOS

Abstract

Abstract-Optimization of SRAM yield using dynamic stability metrics has been evaluated in the past to ensure continued scaling of bitcell size and supply voltage in future technology nodes. Various dynamic stability metrics have been proposed but they have not been used in practical failure analysis and compared with conventional static margins. This work compares static and dynamic metrics to identify expected correlations. A dynamic stability characterization architecture using pulsed word-lines is implemented in 45 nm CMOS to identify sources of variability, and their impact on SRAM stability. Static read margins were observed to overestimate failures by 10-100 X while static write margins failed to predict outliers in critical writeability. Critical writeability was demonstrated to exhibit an enhanced sensitivity to process variations, random telegraph noise (RTN), and negative bias temperature instability (NBTI), compared to static write margins.

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

“…A comprehensive analysis of the effectiveness of assist techniques was performed in [1] using static metrics, which have been shown to be a poor match to silicon failures [2]. Transient simulations are required to quantify the effect of implementation details that have a large effect on failure rates, such as the shape of the boosted wordline waveform.…”

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI

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“…The static noise (SNM) and write (WM) margins metrics are questioned in the low voltage context [6], although they give valuable information regarding the voltage scalability of a bitcell. The Fig.…”

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