2016
DOI: 10.1145/2988233
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Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Abstract: Memory arrays consisting of Static Random Access Memory (SRAM) cells occupy the largest area on chip and are responsible for significant leakage power consumption in modern microprocessors. With the transition from planar Complementary Metal-Oxide-Semiconductor (CMOS) technology to FinFETs, FinFET SRAM design has become important. However, increasing leakage power consumption of FinFETs due to aggressive scaling, width quantization, read-write conflict, and process variations make FinFET SRAM design challengin… Show more

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Cited by 3 publications
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