Characterization of electroless copper as a seed layer for sub-0.1 /spl mu/m interconnects

Gandikota, Srinivas; McGuirk, C.; Padhi, D.; Parikh, S.; Chen, J.; Malik, A. A.; Dixit, G.

doi:10.1109/iitc.2001.930007

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461) 2001

DOI: 10.1109/iitc.2001.930007

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Characterization of electroless copper as a seed layer for sub-0.1 /spl mu/m interconnects

Srinivas Gandikota¹,

C. McGuirk

D. Padhi

et al.

Abstract: Complete gapfill of 0.1 pm features with electroless Cu seed layers and electroplated Cu was demonstrated. Electrical tests on test structures indicated similar line and via chain resistance, yield and line-to-line leakage current on wafers with electroless Cu seed and PVD Cu seed layers filled with electroplated Cu.

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“…[3][4][5] Gandikota et al and Andryuschenko and Reid reported that high-aspect via holes were filled completely by electroplating on a Cu seed layer prepared by physical vapor deposition ͑PVD͒ followed by repair by electroless copper plating. 7,8 However, the processes proved to be too complicated for practical manufacturing.…”

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Characterization of Electroless-Plated Cu Film over Pd Catalytic Layer Formed by an Ionized Cluster Beam

Wang

Shingubara

Sakaue

et al. 2005

J. Electrochem. Soc.

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A continuous electroless-plated Cu film only 10 nm thick was successfully deposited on a TaN barrier over a 1-nm-thick Pd catalytic layer formed by ionized cluster beam deposition. Secondary ion mass spectrometry ͑SIMS͒ analyses for the electrolessplated Cu films on the 20-nm and 1-nm ionized cluster beam ͑ICB͒-Pd layers showed that the Pd metal had diffused into the Cu and caused a high electrical resistivity of Cu interconnect. The electrical resistivity of Cu interconnects formed by electroless plating on an ICB-deposited Pd catalyst layer decreased with decreasing thickness of the ICB-Pd layer. At an ICB-Pd layer thickness of 1-nm, the electrical resistivity of the overlying Cu interconnect was 2.11 ⍀ cm. Moreover, the deposited film has adhesion strength as high as that of sputtered Cu on TaN, even for the case of the 1-nm-thick Pd catalyst layer. A uniform and continuous 10-nm-thick Cu seed layer was formed by electroless plating over a 1-nm-thick Pd layer, and subsequent Cu electroplating filled all high-aspect-ratio via holes without the appearance of voids.Current damascene copper interconnections are fabricated by electroplating on a sputtered Cu seed layer. However, as the dimensions of interconnections continue to shrink, it is becoming increasingly difficult to form a continuous sputtered Cu film on the sidewalls of fine via holes due to the typically poor step coverage of sputtering processes, resulting in the formation of voids during electroplating. 1 Copper electroless plating and chemical vapor deposition ͑CVD͒ are promising processes for the formation of seed layers for subsequent electroplating. 2-6 Copper electroless plating, which does not require a sputtered Cu seed layer, is an efficient means of filling high-aspect-ratio holes and has become increasingly important in the industry. 3-5 Gandikota et al. and Andryuschenko and Reid reported that high-aspect via holes were filled completely by electroplating on a Cu seed layer prepared by physical vapor deposition ͑PVD͒ followed by repair by electroless copper plating. 7,8 However, the processes proved to be too complicated for practical manufacturing.The authors have investigated the formation of a Pd catalysis layer by ionized cluster beam ͑ICB͒ deposition, which provides highly directional deposition suitable for high-aspect-ratio holes. 9 Using this process, a continuous copper layer could be formed even on high-aspect-ratio holes and trenches by electroless copper plating. Furthermore, the adhesion between the electroless-plated Cu film and the TaN barrier layer was sufficient to endure chemical mechanical polishing ͑CMP͒ at an ICB-Pd layer thickness of 20 nm. 10,11 However, the electrical resistivity of the Cu damascene interconnection was rather high ͑3.5-3.9 ⍀ cm͒, thought to be due to diffusion of Pd into the overlying Cu. In this study, the effect of the thickness of the ICB-Pd layer on the properties of the overlying electroless-deposited Cu film is investigated. ExperimentalICB-Pd films with thickness of 1-20 nm were deposited on t...

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mentioning

confidence: 99%

Characterization of Electroless-Plated Cu Film over Pd Catalytic Layer Formed by an Ionized Cluster Beam

Wang

Shingubara

Sakaue

et al. 2005

J. Electrochem. Soc.

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Electroless processes for micro- and nanoelectronics

Shacham‐Diamand

Inberg

Sverdlov

et al. 2003

Electrochimica Acta

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Bottom-Up Fill of Copper in Deep Submicrometer Holes by Electroless Plating

Shingubara

Wang

Yaegashi

et al. 2004

Electrochem. Solid-State Lett.

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Bottom-up fill of Cu in deep submicrometer via holes was achieved through electroless plating alone for the first time. We investigated the effect of addition of inhibitor molecules to electroless Cu plating solution, and found that sulfopropyl sulfonate ͑SPS͒ was highly effective in promoting the bottom-up fill. The tendency for bottom-up filling was enhanced by shrinkage of the hole diameter. This suggests that the diffusion flux of SPS molecules to the bottom of holes was more suppressed for smaller holes. Thus, the Cu deposition rate near the hole bottom is larger than that outside the hole, leading to bottom-up filling.

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Characterization of electroless copper as a seed layer for sub-0.1 /spl mu/m interconnects

Cited by 3 publications

References 3 publications

Characterization of Electroless-Plated Cu Film over Pd Catalytic Layer Formed by an Ionized Cluster Beam

Characterization of Electroless-Plated Cu Film over Pd Catalytic Layer Formed by an Ionized Cluster Beam

Electroless processes for micro- and nanoelectronics

Bottom-Up Fill of Copper in Deep Submicrometer Holes by Electroless Plating

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