Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C

Nurvitadhi, Eriko; Chalainanont, Nirut; Lu, Shih-Lien

doi:10.1145/1088149.1088152

Cited by 6 publications

(3 citation statements)

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“…[10] used an FPGA based cache model that connects directly to the front-side bus to understand the L3 cache behavior. [11] did the characterization of the memory system behavior using performance counters, SimOS simulation environment as well as the ATOM.…”

Section: Related Workmentioning

confidence: 99%

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Using GPU to accelerate a pin-based multi-level cache simulator

Han

Gao

Long

et al. 2010

Proceedings of the 2010 Spring Simulation Multiconference

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Trace-driven simulation methodology is the most widely used method to evaluate the design of future computer memory architecture. Since this methodology demands large amounts of storage and computer time, there is a growing need for simulation methodologies to determine the memory system requirements of emerging workloads in a reasonable amount of time. Several techniques have been proposed to reduce the space that store memory reference and improve the performance of sequential trace-driven simulation. This paper presents the use of binary instrumentation as the memory reference generator and parallel simulation technique that based on the generic graphics processing unit (GPU). One way to achieve fast parallel simulation is to simulate the independent sets of a cache concurrently on different compute resource, but results show that this method is not efficient because of a high correlation of the activity between different sets. To put parallelism to effective use, we show that a multi-configuration simulation in single pass method gains 2.44x performance improvement compared to traditional sequential algorithm.

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Section: Related Workmentioning

confidence: 99%

“…As shown in figure 4, we use 10 bits as the key's length to implement the sort algorithm, which means the number of keys is 2 10 . We can sort 1024 sets' references.…”

Section: Using Radix Sort Based On Gpumentioning

confidence: 99%

Using GPU to accelerate a pin-based multi-level cache simulator

Han

Gao

Long

et al. 2010

Proceedings of the 2010 Spring Simulation Multiconference

View full text Add to dashboard Cite

show abstract

“…Chodneker et al analyzed the time distribution and locality of communication events in some message-passing and shared-memory applications [20]. Nurvitadhi et al used an FPGA-based cache model (PHA$E) that connects directly to the front-side bus to analyze the shared vs. private L3 cache behavior of SPECjAppServer and TPC-C [26].…”

Section: Related Workmentioning

confidence: 99%