Characterization of pixel sensor designed in 180 nm SOI CMOS technology

Abstract

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

An lpGBT subsystem for environmental monitoring of experiments

“…The output of the DAC resistor ladder is buffered to improve its current efficiency. An existing design with 12-bit input control and non-rail-to-rail output buffer was used to achieve the requested 10-bit resolution [17].…”

MAPS sensor for radiation imaging designed in 180 nm SOI CMOS technology

“…X-CHIP-02 contains a number of test-structures, for example separate sensor diodes to determine their leakage current, capacitance and an array of transistors for radiation testing. Their evaluation is described in a separate publication [9].…”

“…Signal response of 100 µm pixel is attenuated and suffers from significantly higher noise compared to 50 µm pixel. The noise difference is not fully understood and it can be partially explained by the larger capacitance of the sensor diode (2.9 fF of the 50 µm pixel and 4.8 fF of the 100 µm pixel [9]). Noise level of 50 µm pixels ranges from 40 to 50 electrons (depending on the signal amplitude) and is slightly higher, than noise level obtained from circuit simulations performed at schematic level as shown in 2018 JINST 13 C06004 figure 5.…”

X-ray characterization of BUSARD chip: A HV-SOI monolithic particle detector with pixel sensors under the buried oxide

“…The success of these devices was leveraged by the progress 2021 JINST 16 P12030 of the SOI technology, which made possible the fabrication of wafers with less defects both in the thin silicon film and in the handle wafer [10]. More recently, several works [12][13][14][15][16][17][18] presented the design and characterization of a MAPS on a 180 nm PD-SOI fabrication process which exploits the buried oxide to isolate the sensor device from the active electronics, connecting both through a hole in the BOX. These works include the description of the design and several tests like radiation hardness, charge collection in the sensitive junction, Total Ionizing Dose (TID) and even Single Event Effect (SEU) tolerance.…”