Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation Results

Ding, Luchang; Cai, Chang; Chen, Gengsheng; Wu, Zehao; Zhang, Jing; Wu, Chang; Yu, Jun

doi:10.1109/iscas48785.2022.9937652

Cited by 5 publications

(3 citation statements)

References 17 publications

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“…Micromachines 2023, 14, x FOR PEER REVIEW 7 of 14 Therefore, the RHB-12T-hardened cell has the ability of single-node Q (or QN), S0, S1, and double-node {S0, S1} to upset and recover and can completely suppress SNU and partially tolerate DNU response. The research shows that the charge-sharing effect between two NMOS (or PMOS-NMOS) occurs at 1.62 µm (or 0.6 µm) [28,29]. The physical distance between node Q and nodes S0 and S1 is reasonably designed on the layout to effectively reduce the influence of the charge-sharing effect.…”

Section: Seu Recovery Analysismentioning

confidence: 99%

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications

Yao

Zhang

et al. 2023

Micromachines

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The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE). Therefore, a 12T SRAM-hardened circuit (RHB-12T cell) for the soft error recovery is proposed using the radiation hardening design (RHBD) concept. To verify the performance of the RHB-12T, the proposed cell is simulated by the 28 nm CMOS process and compared with other hardened cells (Quatro-10T, WE-Quatro-12T, RHM-12T, RHD-12T, and RSP-14T). The simulation results show that the RHB-12T cell can recover not only from single-event upset caused by their sensitive nodes but also from single-event multi-node upset caused by their storage node pairs. The proposed cell exhibits 1.14×/1.23×/1.06× shorter read delay than Quatro-10T/WE-Quatro-12T/RSP-14T and 1.31×/1.11×/1.18×/1.37× shorter write delay than WE-Quatro-12T/RHM-12T/RHD-12T/RSP-14T. It also shows 1.35×/1.11×/1.04× higher read stability than Quatro-10T/RHM-12T/RHD-12T and 1.12×/1.04×/1.09× higher write ability than RHM-12T/RHD-12T/RSP-14T. All these improvements are achieved at the cost of a slightly larger area and power consumption.

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Section: Seu Recovery Analysismentioning

confidence: 99%

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications

Yao

Zhang

et al. 2023

Micromachines

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“…Consequently, the use of tools that allow designers to locate sensitive nodes and harden circuits before radiation tests is an interesting approach to increase the robustness of electronics for harsh-radiation environments. Whereas there are exhaustive analyses of charge sharing employing 3D simulation tools such as TCAD [16] or from a more physical perspective [17], this paper focuses on a complementary approach that optimizes the time required to find vulnerabilities against radiation in designed circuits. The proposed methodology is based on a tool, called AFTU [18], which uses electrical models to emulate particle impacts with a certain level of charge, allowing fast analyses based on transient simulations to provide RHbD circuits [19,20].…”

Section: Jinst 18 P10023mentioning

confidence: 99%

Design optimization of a Dual-Interlocked-Cell in 65 nm CMOS tolerant to Single Event Upsets

Márquez,

Palomo,

Muñoz

et al. 2023

J. Inst.

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Dual-Interlocked-Cell (DICE) latches are tolerant to Single Event Effects (SEE) by design owing to intrinsic redundancy. In nanometric technologies, as in the 65 nm scale, there are new SEE vulnerabilities associated with charge sharing between nodes. Herein we present a systematic analysis of the robustness against radiation using a simulation software tool for analog and mixed-signal circuits (AFTU) that emulates the possible effects generated by particle impacts. In this paper, we evaluate the influence of SEE on circuit performance using this tool as an RHbD assessment for designers. An exhaustive study of the possible vulnerabilities of the DICE architecture is performed, including an evaluation of the proximity between critical nodes at the layout level. As a result, we propose several modifications to the cell implementation to optimize its robustness against Single Event Upsets (SEU). An assortment of five designs with different variations of the original DICE scheme was sent for fabrication on a new chip and tested under ion beams, with promising results showing a clear improvement in the SEU sensitivity of the cell. The best results come from a redesign of the load circuitry to avoid a SET2SEU effect and full interleaved layout to avoid charge sharing effects after a single event.

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“…However, for the top silicon layer, the electrons and holes generated by the incident device can move through the shared active region, enabling charge sharing. Furthermore, experimental results [ 18 ] also demonstrate the existence of charge-sharing effects in FDSOI SRAM. This indicates that the decrease in the LET upset threshold observed in device level simulations of SRAM is a result of the combined effects of charge sharing and bipolar amplification.…”

Section: Sram Device Level See Simulationmentioning

confidence: 99%

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect

Yin,

Gao,

Wei

et al. 2023

Micromachines

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In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device-level simulation. The results demonstrate that, under the combined influence of these two effects, the circuit’s upset threshold and critical charge decreased by 15.4% and 23.5%, respectively. This indicates that the charge sharing effect exacerbates the single event effects. By analyzing the incident conditions of two different incident radius particles, it is concluded that the particles with a smaller incident radius have a worse impact on the SRAM circuit, and are more likely to cause the single event upset in the circuit, indicating that the ionization distribution generated by the incident particle affects the charge collection.

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Characterization of Single Event Upsets of Nanoscale FDSOI Circuits Based on the Simulation and Irradiation Results

Cited by 5 publications

References 17 publications

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications

Design optimization of a Dual-Interlocked-Cell in 65 nm CMOS tolerant to Single Event Upsets

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect

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