Characterization of single photon avalanche diodes fabricated by 0.13μm CMOS technology

Abstract

In this paper, two different SPAD structures are designed and fabricated by 0.13μm CMOS technology. For the structure-1, a guard ring with low implanted p-well is used at the edge of p + region, which prevents the periphery region breakdown while for the structure-2 a "virtual" guard ring structure with a p -well under the whole P + region is designed.The first structure exhibits a maximum photon detection probability of 15% and a typical dark count rate of 18 kHz at room temperature while the second structure exhibits a maximum of photon detection probability of 28% and a dark count rate of 23 kHz. These results would give a help for further advanced SPAD design.CMOS, SPAD, dark count rate, photon detect efficiency.