Characterization of symmetrical spiral inductor in 0.35 μm CMOS technology for RF application

Teo, T. Hui; Choi, Yeung-Bun Choi Yeung-Bun; Liao, Huailin; Xiong, Yujie; Fu, Jianqin

doi:10.1016/j.sse.2004.04.004

Cited by 26 publications

(24 citation statements)

References 7 publications

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“…21, we will get V 18 ¼ ÀV 21 ; V 17 ¼ ÀV 22 ; V 16 ¼ ÀV 23 , and V 15 ¼ ÀV 24 . For an easy comparison and to comply with the notations of the stack and the MPS inductors, we can approximate that, A 1 % ða 1 þ a 8 Þ; A 2 % ða 2 þ a 7 Þ; A 3 % ða 3 þ a 6 Þ and A 4 % ða 4 þ a 5 Þ where A 1 ; A 2 ; A 3 and A 4 represent the total area of the spiral full turn 1, 2, 3 and 4.…”

Section: Resultsmentioning

confidence: 99%

“…The quality factor and the self resonant frequency are more or less comparable. However the area of MPS inductor is smaller by 72.9 and 78.4% compared to symmetrical inductors of [11] and [24], respectively. Therefore, the inductance to area ratio is also higher by more than 300%.…”

Section: Comparison Of Area and Performance Of Mps With Its Equivalenmentioning

confidence: 91%

“…The MPS inductor is compared to the conventional planar symmetric inductors of [11] and [24]. The results are summarized in Table 3.…”

Section: Comparison Of Area and Performance Of Mps With Its Equivalenmentioning

confidence: 99%

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Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

Haobijam

Paily

2009

Analog Integr Circ Sig Process

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This paper presents the design of a multilevel pyramidically wound symmetric (MPS) inductor structure. Being multilevel, the MPS inductor achieves high inductance to area ratio and hence occupies smaller silicon area. The symmetric inductor is realized by winding the metal trace of the spiral coil down and up in a pyramidal manner exploiting the multilevel VLSI interconnects technology. Closed form expressions are also developed to estimate the self resonating frequency (f res ) of the MPS inductor and results are compared to two layer conventional symmetric and asymmetric stack. The estimation is also validated with full wave electromagnetic simulation. The performance of various MPS inductors of different metal width, metal offsets and outer diameter is demonstrated. For an inductance of 8 nH, the MPS inductor reduces the area by 65-95% over conventional planar symmetric inductors and 71-94% over its equivalent pair of asymmetric planar inductors. The performance is also compared to other symmetric inductors reported in literature. With MPS inductor, the cost and size of RF IC's will be reduced significantly.

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Section: Resultsmentioning

confidence: 99%

Section: Comparison Of Area and Performance Of Mps With Its Equivalenmentioning

confidence: 91%

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Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

Haobijam

Paily

2009

Analog Integr Circ Sig Process

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“…These loss effects include conductor skin effect, proximity effect and loss in the silicon substrate. Therefore we employ the double-p network topologies for the center-tapped symmetric spiral inductors [3,4].…”

Section: Double-p Equivalent Circuit Modelmentioning

confidence: 99%

Modeling of double-π equivalent circuit for on-chip symmetric spiral inductors

Tang

Liu

Zhang

et al. 2008

Solid-State Electronics

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“…VCO is optimized by considering the trade-off between power consumption, output power, and low phase noise [7]. Programmable VCO is needed to maintain a stable VCO gain for wide frequency range [8].…”

Section: Subblocks Designmentioning

confidence: 99%

Fully integrated frequency synthesizer design for wireless network application with digital programmability

Teo

Tan

2007

Micro & Optical Tech Letters

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A 2.60‐GHz integer‐N frequency synthesizer was designed and implemented in SiGe BiCMOS technology. The single chip includes fully integrated VCO (voltage control oscillator) as well as LPF (loop‐filter). The synthesizer provides a wide frequency range of 300 MHz, which covers 2.59–2.66 and 2.8725–2.9025 GHz, with a single VCO. Digital technique is employed at VCO and charge‐pump to cover the frequency range and cater for process variation. Using reference frequency of 2.5 MHz, the fabricated prototype demonstrates a settling time of 32 μs, and reference spur below −56 dBc. The synthesizer's phase noise is −115 dBc/Hz at 1.0‐MHz offset frequency. It consumes approximately 42 mW power from a 3.0 V single supply, with a total active area of 2.34 mm2. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2579–2582, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22773

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Characterization of symmetrical spiral inductor in 0.35 μm CMOS technology for RF application

Cited by 26 publications

References 7 publications

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

Modeling of double-π equivalent circuit for on-chip symmetric spiral inductors

Fully integrated frequency synthesizer design for wireless network application with digital programmability

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