Characterization Scheme for III-V Junction Development

Abstract

This work introduces a characterization scheme for junction development of conventional inversion mode bulk MOSFETs with novel III-V substrates, that effectively reduces the cost and development cycle. The scheme is composed of high resolution X-ray diffraction (HRXRD), Raman spectroscopy, secondary ion mass spectrometry (SIMS), and Hall measurements to monitor substrate thickness, composition, crystal quality, mobility, sheet resistance, and dopant activation. We applied this scheme to optimize the post-Si implant activation temperature, study the thermal stability of III-V substrates, and evaluate the impact of a fluorine (F) co-implant. Results show that the optimal post-implant rapid thermal anneal is about 750oC; a flash anneal for III-V should be kept below 900oC. F co-implantation reduces the junction depth but degrades the efficacy of dopant activation.