Silicon photonics has been heralded for a number of high technology fields, but access to a high quality technology has been limited to vertically integrated design/fabrication companies, or fabless companies with significant resources to engage high volume fabs. More recently, research and development hubs have developed and released process design kits and multi-project wafer programs to lower the barrier. We present the first silicon photonics multi-project wafer (MPW) service produced in a state-of-the-art 300 mm fabrication facility. The MPW service is enabled by a best-in-class process design kit (PDK) which allows designers to layout and obtain photonic integrated circuits (PICs) that work properly on the first run. The fabrication of these circuits is carried out at the SUNY Polytechnic Institute which operates a world class 300 mm cleanroom that, besides silicon photonics, develops sub-7 nm CMOS architectures. The industrial-level management of this facility and its equipment provides high quality photonic devices which are repeatable from run-to-run along with rapid turnaround time. The devices that are available to designers via the process design kit are produced by Analog Photonics and have been verified on actual runs. The performance of these devices is comparable to the state-of-the-art and enables a wide variety of silicon photonic applications. Index Terms-Photonic integrated circuits, silicon photonics, foundries. I. INTRODUCTION O VER the past twenty years the popularity of silicon photonic integrated circuits (PICs) has increased as their reported performance improves. This popularity is partially driven due to the potential cost benefits that silicon-based PICs possess over alternative material platforms (ie, III-V). Specifically, PICs fabricated using a silicon-based platform are able to take advantage of the unsurpassed infrastructure of silicon-based electronic Manuscript

A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs). This development platform yields 1000s of functional photonic components as well as 16M transistors per chip module. The transmitter operates at 6Gb/s with an energy cost of 100fJ/bit and the receiver at 7Gb/s with a sensitivity of 26µA (-14.5dBm) and 340fJ/bit energy consumption. A full 5Gb/s chip-to-chip link, with the on-chip calibration and self-test, is demonstrated over a 100m single mode optical fiber with 560fJ/bit of electrical and 4.2pJ/bit of optical energy.

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We demonstrate a novel fiber-to-chip coupling scheme based on surface-normal free-form micro-reflectors 3D-printed onto SiNx waveguide facets. Insertion losses of 0.5 dB and 1 dB bandwidth exceeding 300 nm were measured at 1550 nm wavelength.