Power systems for modern complementary metaloxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.

Abstract-3D integrated circuit technology with through-silicon vias offers many advantages include improved form factor, increased circuit performance, robust heterogenous integration and reduced costs. Waferto-wafer integration supports the highest possible density of throughsilicon vias and highest throughput; however, in contrast to die-to-wafer integration, it does not benefit from the ability to bond only tested and diced good die. In wafer-to-wafer integration, wafers are entirely bonded together, which can unintentionally integrate a bad die from one wafer to a good die from another wafer reducing the yield. In this paper we propose solutions that maximize the yield of wafer-towafer 3D integration, assuming that the individual die can be tested on the wafers before bonding. We exploit some of the available flexibility in the integration process, and propose wafer assignment algorithms that maximize the number of good 3D ICs. Our algorithms range from scalable, fast heuristics to optimal methods that exactly maximize the yield of wafer-to-wafer 3D integration. Using realistic defect models and yield simulations, we demonstrate the effectiveness of our methods up to large numbers of wafer stacks. Our results demonstrate that it is possible to significantly improve the yield in comparison to yield-oblivious wafer assignment methods.

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Goat conceptuses were surgically removed from the uterus at different days during early pregnancy and cultured for 24-30 h in the presence of L-[3H]leucine to determine the effects of embryo removal on the interestrus interval and to characterize in vitro synthesis and release of conceptus proteins. Normal cyclic and animals (controls) exhibited interestrus intervals of 20.44 +/- 0.89 days. Removal of conceptuses on Days 13 and 15 did not alter interestrus intervals compared to cyclic animals. Removal of conceptuses on Day 17 and times thereafter resulted in significant (p less than 0.05) prolongation of interestrus intervals. These results demonstrate that maternal recognition of pregnancy in the goat occurs between Days 15 and 17. Proteins synthesized and released into the medium by conceptuses were first detectable at Day 16 by the analytical method employed (two-dimensional polyacrylamide gel electrophoresis followed by fluorography). The major protein synthesized at this time was acidic (pI = 5.2-5.7) and consisted of two isotypes with molecular weights of about 17,000. Although patterns of protein production became more complex with conceptus development, this protein remained as a major product through Day 21 but not afterwards. This protein, as well as two other low molecular weight acidic proteins (Mr approximately equal to 21,000, 23,000; pI = 5.7-6.0) were shown by immunoprecipitation to react with anti-ovine trophoblast protein-1 (oTP-1) serum. Hence, these products may comprise a caprine trophoblast protein-1 (cTP-1) complex.(ABSTRACT TRUNCATED AT 250 WORDS)

CMOS circuits on printed circuit boards with continuous power planes require decoupling capacitors to keep power supply witliin specification, provide signal integrity and reduce ERlC/EMI radiated noise. Capacitor values and quantities are mlculated using time and frequency domain techniques. 0-7803-2411-0/94/$4.00 @ 1994 IEEE Symposium on Electromagnetic Conpatibiliry , 1993. Decoupling capacitors are used to keep the power supply within specification at low frequencies, for signal integrity near the clock frequency and to reduce EM1 radiation at high frequencies. Several values of capacitors are required to accomplish this. The capacitance required near the clock frequency is determined by time domain calculations and the capacitance required at other frequencies is determined by circuit simulation in the frequency domain. Target impedances for acceptable performance are calculated