Power distribution system design methodology and capacitor selection for modern CMOS technology

2007 IEEE/ACM International Conference on Computer-Aided Design

Secareanu³

et al. 2007

Abstract-Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on the die based on an unsystematic or ad hoc approach. In this way, large decoupling capacitors are often placed at a significant distance from the current load, compromising the signal integrity of the system. This issue of power delivery cannot be alleviated by simply increasing the size of the on-chip decoupling capacitors. To be effective, the on-chip decoupling capacitors should be placed physically close to the current loads. The area occupied by the onchip decoupling capacitor, however, is directly proportional to the magnitude of the capacitor. The minimum impedance between the on-chip decoupling capacitor and the current load is therefore fundamentally affected by the magnitude of the capacitor.A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed onchip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. An analytic solution is shown to provide accurate distributed system. The worst case error is 0.003% as compared to SPICE. Techniques presented in this paper are applicable not only for current technologies, but also provide an efficient placement of the onchip decoupling capacitors in future technology generations.

Section: Placing On-chip Decoupling Capacitorsmentioning

confidence: 99%

Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs

Попович

2007 IEEE/ACM International Conference on Computer-Aided Design

Secareanu³

et al. 2007

“…Decoupling capacitors are therefore also widely used as a local reservoir of charge which are self activated and supply current when the power supply level deteriorates [8]. Inserting decoupling capacitors into the power distribution network is a natural way to lower the power grid impedance at high frequencies [4]. Tens of on-chip power supplies, hundreds-to-thousands of on-chip decoupling capacitors, and millions-to-billions of active transistors are anticipated in the design of next generation high performance integrated circuits [9].…”

Section: Introductionmentioning

confidence: 99%

“…Due to the self-and mutual inductance of the power lines, the power grid impedance increases with frequency [1]. Lowering the target impedance of the power distribution network has therefore become increasingly important [4]. Multiple decoupling capacitors are placed on-chip to provide local charge to the load circuitry, effectively reducing the impedance between the power supplies and load circuits [5].…”

Section: Introductionmentioning

confidence: 99%

Distributed power network co-design with on-chip power supplies and decoupling capacitors

Köse

International Workshop on System Level Interconnect Prediction

2011

Abstract-With each technology generation, the power delivery network becomes larger and more complicated, making the system analysis process computationally complex. The rising number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. Interactions among the on-chip power supplies, decoupling capacitors, and load circuitry are investigated in this paper. The on-chip power supplies and decoupling capacitors within the power network are simultaneously co-designed and placed. The effect of physical distance on the power supply noise is investigated. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.

“…Focusing on power networks, supply network impedance is a primary issue [5]. The size and placement of the decoupling capacitors are also important [6].…”

Section: Introductionmentioning

confidence: 99%

Globally integrated power and clock distribution network

Jakushokas

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

2010

Abstract-The global networks within a conventional integrated circuits (IC) consists of three major types: power, ground, and clock networks. These three networks consumes most of the metal resources in the highest metal layers. The signals traversing the power and clock distribution networks are fundamentally different in terms of signal frequency and current flow. Combining the power and clock network into a globally integrated network is therefore possible. In this paper, the general concept of a globally integrated power and clock (GIPAC) system is proposed. The circuitry supporting this GIPAC system is also presented. Simulation results based on a 90 nm CMOS technology demonstrate the potential of GIPAC.