Characterization, simulation, and modeling of FET source/drain diffusion resistance

Lu, Ning; Dewey, B.

doi:10.1109/cicc.2008.4672076

2008 IEEE Custom Integrated Circuits Conference 2008

DOI: 10.1109/cicc.2008.4672076

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Characterization, simulation, and modeling of FET source/drain diffusion resistance

Ning Lu¹,

B. Dewey

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Cited by 2 publications

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Modeling of resistance in FinFET local interconnect

Kotecha

Wachnik

2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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We present an innovative and comprehensive approach to model the resistance of local interconnect used in finFET technologies. Our parasitic resistance formulas for finFET source/drain regions cover both merged and unmerged fin processes. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in 14nm finFET technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.

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Modeling of resistance in FinFET local interconnect

Kotecha

Wachnik

2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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Symmetry breaking in the drain current of multi-finger transistors

Lee

Wachnik

2015

2015 IEEE Custom Integrated Circuits Conference (CICC)

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Characterization, simulation, and modeling of FET source/drain diffusion resistance

Cited by 2 publications

References 6 publications

Modeling of resistance in FinFET local interconnect

Modeling of resistance in FinFET local interconnect

Symmetry breaking in the drain current of multi-finger transistors

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