Characterizing and Modelling Common Mode Inductors at high Current Levels for System ESD Simulations

Ammer, Michael; Miropolskiy, Sergey; Rupp, Andreas; Nieden, Friedrich zur; Sauter, Martin; Maurer, Linus

doi:10.23919/eos/esd.2019.8870005

Cited by 7 publications

(3 citation statements)

References 5 publications

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“…1 clearly depicts both the direct and indirect test setup. However, CM chokes are not designed to handle the large currents that a system-level ESD event produces [16]. The core saturation effect at high currents in CM inductive chokes has previously been found to cause unexpectedly low system-level ESD failure levels [14], [16].…”

Section: Choke Saturation Problems Under High Current Esd Stressmentioning

confidence: 99%

“…However, CM chokes are not designed to handle the large currents that a system-level ESD event produces [16]. The core saturation effect at high currents in CM inductive chokes has previously been found to cause unexpectedly low system-level ESD failure levels [14], [16]. Table I presents the IEC test results for the direct and indirect tests.…”

Section: Choke Saturation Problems Under High Current Esd Stressmentioning

confidence: 99%

“…Mutual ballasting technique is proposed to mitigate multifinger turn-on problems. The high current saturation of choke was also demonstrated in [16] with transmission line pulse (TLP) stressing the choke alone. Though the mutual ballasting proposed in [14] improves the device IEC performance with uniform turn-on across all fingers, however, it is found that problem still persists with very narrow and sporadic failure window.…”

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confidence: 99%

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System-Level IEC ESD Failures in High-Voltage DeNMOS-SCR: Physical Insights and Design Guidelines

Kranthi

Sarro

Sankaralingam

et al. 2021

IEEE Trans. Electron Devices

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A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure. Index Terms-Current filaments, drain-extended nMOS [laterally double diffused MOS (LDMOS)], electrostatic discharge (ESD), International Electrotechnical Commission (IEC), system-level ESD. I. INTRODUCTIONT HE electrostatic discharge (ESD) protection design is particularly challenging in automotive applications because product requirements often dictate qualification for a variety of stress models in addition to human body model (HBM) and charge device model (CDM). For example, the communication Manuscript

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Section: Choke Saturation Problems Under High Current Esd Stressmentioning

confidence: 99%