Characterizing STI CMP Processes with an STI Test Mask Having Realistic Geometric Shapes

Abstract

Chemical mechanical polishing (CMP) has become the enabling planarization method for shallow trench isolation (STI) of sub 0.25μm technology. CMP is able to reduce topography over longer lateral distances than earlier techniques; however, CMP still suffers from pattern dependencies that result in large variation in the post-polish profile across a chip. In the STI process, insufficient polish will leave residue nitride and cause device failure, while excess dishing and erosion degrade device performance.Our group has proposed several chip-scale CMP pattern density models [1], and a methodology using designed dielectric CMP test mask to characterize CMP processes [2]. The methodology has proven helpful in understanding STI CMP; however, it has several limitations as the existing test mask primarily consists of arrays of lines and spaces of large feature size varying from 10 to 100 μm. In this paper, we present a new STI characterization mask, which consists of various rectangular, L-shape, and X-shape structures of feature sizes down to submicron. The mask is designed to study advanced STI CMP processes better, as it is more representative of real STI structures. The small feature size amplifies the effects of edge acceleration and oxide deposition bias, and thus enables us to study their impact better. Experimental data from an STI CMP process is shown to verify the methodology, and these secondary effects are explored. The new mask and data guide ongoing development of improved pattern dependent STI CMP models.

Detailed Placement for Enhanced Control of Resist and Etch CDs

“…Due to the high-density-plasma process, which is widely used for oxide deposition, the oxide is deposited with slanted sidewalls. Hence, features on the oxide layer are a shrunk version of the nitride features [3], [48], [69]. For example, a square feature on the nitride layer with sides of 5x could correspond to a square with sides of 3x when deposited on the oxide layer-i.e., each edge is brought in by distance x.…”

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction

“…However, the real goal of fill insertion is improved post-CMP planarity so it is important to assess that. We use the STI CMP simulator developed and calibrated by MIT's MTL group [7,10] to predict post-CMP topography. Typical values are used for the initial structure and CMP modelL parameters such as planarization length, pad bending, slurry selectivity, etc.…”

“…Often this approach is used to control only the nitride density along with reverse etchback which controls the oxide density. Beckage et al proposed a model-based fill insertion methodology that uses CMP simulation, an area of active research [3,7,10], to identify regions for fill insertion [2]. Their approach uses two types of fill "tiles": (I) tiles that contribute to the nitride density but negligibly to the oxide density, and (2) tiles that contribute to both, oxide and nitride densities.…”

“…For high density plasma (HDP) oxide deposition, which is the mainstream oxide deposition technology, the deposition profile exhibits a slanted sidewall. Consequently, features on the oxide layer appear as shrunk nitride features [3,9,10]. Specifically, a nitride polygon is shrunk or sized down by a fixed amount (denoted by u.)…”

Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement

“…Topography simulation was the focus of several recent papers, e.g., [20] and [22]. These works present and calibrate analytical models that account for the underlying pattern and various CMP process parameters, such as planarization length, pad bending, slurry selectivity, etc., to predict the post-CMP thickness variation at all locations of a chip.…”