Characterizing the memory behavior of compiler-parallelized applications

Torrie, Evan; Martonosi, Margaret; Tseng, Chau‐Wen; Hall, Mary

doi:10.1109/71.553272

Cited by 20 publications

(10 citation statements)

References 21 publications

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“…To improve memory hierarchy performance, various manual and automated optimization techniques have been developed for uniprocessors and parallel systems [9]- [11]. To exploit the spatial and temporal locality [12] properties, the data access order is changed by reordering the computation.…”

Section: A Memory Hierarchy Performance Optimizationsmentioning

confidence: 99%

Dynamic Data Layouts for Cache-Conscious Implementation of a Class of Signal Transforms

Park

Prasanna

2004

IEEE Trans. Signal Process.

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Abstract-Effective utilization of cache memories is a key factor in achieving high performance for computing large signal transforms. Nonunit stride access in the computation of large signal transforms results in poor cache performance, leading to severe degradation in the overall performance. In this paper, we develop a cache-conscious technique, called a dynamic data layout, to improve the performance of large signal transforms. In our approach, data reorganization is performed between computation stages to reduce cache misses. We develop an efficient search algorithm to determine an optimal tree with the minimum execution time among possible factorization trees based on the size of the signal transform and the data access stride. Our approach is applied to compute the fast Fourier transform (FFT) and the Walsh-Hadamard transform (WHT). Experiments were performed on Alpha 21264, MIPS R10000, UltraSPARC III, and Pentium 4. Experimental results show that our FFT and WHT achieve performance improvement of up to 3.52 times over other state-of-the-art FFT and WHT packages. The proposed optimization is portable across various platforms.

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Section: A Memory Hierarchy Performance Optimizationsmentioning

confidence: 99%

Dynamic Data Layouts for Cache-Conscious Implementation of a Class of Signal Transforms

Park

Prasanna

2004

IEEE Trans. Signal Process.

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“…Many systematic software-oriented memory management approaches exist in literature but they do not focus on the combination of performance and overall power, 'partly sponsored by the Esprit ESDLPD project 25518 : DAB-LP 0-7803-5650-0/99/$10.00 0 1999 IEEE which is vital as motivated above [23]. In terms of hardware-orientedmemory management, most approaches focus on scalar signals.…”

Section: Context and Motivationmentioning

confidence: 99%

Parametrizable behavioral IP module for a data-localized low-power FFT

Brockmeyer

Ghez²,

D'Eer³

et al.

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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FFTs are important modules in embedded telecom systems, many of which require low-power real-time implementations. This paper describes a technique for aggressively localizing data accesses in a (inverse) Fast Fourier 'hansformation at the source code level. The global I/O functionality is not modified and neither is the bittrue arithmetic behavior. 'Qpically 20 to 50% of the background memory accesses can be saved. A heavily parametrizable solution will be proposed which leads to a family of power optimized algorithm codes. Moreover, efficient coding details for specific instances are shown. CONTEXT AND MOTIVATIONA hardware or even an embedded software realization has to be power efficient in order to reduce the size of the chip packages (where it is embedded) or the battery (if used in a mobile application) 141. The power cost in data-dominated application is heavily dominated by storage and transfers of complex data types. This has been demonstrated both for custom [18] and for programmable instruction-set processors 1141. The reason is that an off-chip data transfer consumes about 33 times more power than a typical 16-bit arithmetic operation like an addition.In addition experiments indicate that the number of primitive arithmetic operations is typically only a few times higher than the number of data transfer operations to big signals. Combined this gives at least a factor of 10 in difference for the power consumption of data transfers in an unoptimized description compared to (equally unoptimized) arithmetic operations. Similar observations can be made for the FIT function in both software and especially hardware implementations. Hence the global data transfer and storage overhead should be reduced first in the system design trajectory.To perform the high performance data dominated function, fast busses and large memories with high access rates ftodto data-path are needed. Efficient implementation of the complex algorithms requires a global analysis of the critical sections and code transformations to eliminate or at least alleviate the impact of these bottlenecks.Many systematic software-oriented memory management approaches exist in literature but they do not focus on the combination of performance and overall power, 'partly sponsored by the Esprit ESDLPD project 25518 : DAB-LP 0-7803-5650-0/99/$10.00 0 1999 IEEE 63 5

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“…Various manual and automated memory access optimization techniques have been developed for uniprocessors and parallel systems [8,10,15]. Access reordering involves modification of the computation to change the order in which data is accessed.…”

Section: Memory Access Optimizationsmentioning

confidence: 99%

“…15 points can fit in the cache. As the number of FFT points increases from 2 14 to 2 16 , the Miss rates for a single precision 256K-point FFT with various cache block sizes…”

mentioning

confidence: 99%

Dynamic data layouts for cache-conscious factorization of DFT

Park

Kang

Bondalapati

et al.

Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000

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Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimization techniques for computing the DFT rely on either modifying the computation and data access order or exploiting low level platform specific details, while keeping the data layout in memory static. In this paper, we propose a high level optimization technique, dynamic data layout (DDL). In DDL, data reorganization is performed between computations to effectively utilize the cache. This cache-conscious factorization of the DFT including the data reorganization steps is automatically computed by using efficient techniques in our approach. An analytical model of the cache miss pattern is utilized to predict the performance and explore the search space of factorizations. Our technique results in up to a factor of 4 improvement over standard FFT implementations and up to 33% improvement over other optimization techniques such as copying on SUN UltraSPARC-II, DEC Alpha and Intel Pentium III.

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Characterizing the memory behavior of compiler-parallelized applications

Cited by 20 publications

References 21 publications

Dynamic Data Layouts for Cache-Conscious Implementation of a Class of Signal Transforms

Dynamic Data Layouts for Cache-Conscious Implementation of a Class of Signal Transforms

Parametrizable behavioral IP module for a data-localized low-power FFT

Dynamic data layouts for cache-conscious factorization of DFT

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