Characterizing the spatio-temporal qubit traffic of a quantum intranet aiming at modular quantum computer architectures

Abstract

Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects.

Mapping Quantum Circuits to Modular Architectures with QUBO

“…• Differentiating between remote two-qubit gates (operations between two separate qubits in different cores) and qubit state transfers. This will help to better optimize the amount of inter-core communication, by doing the qubit transfers only when necessary, and also make more realistic multi-core architecture when combined with investigating other inter-core communication links [25,27]. • Solving the scalability limitations related to circuit depth by decreasing the number of decision variables via an alternative problem formulation to a gate assignment version instead of the qubit assignment.…”

“…Classical links are required to assist core coordination and job distribution [26]. The architectural complexity involving the communication channels and traffic make it more difficult to perform quantum circuit mapping when compared with mapping to single-core devices [27,28].…”

Interconnect Fabrics for Multi-Core Quantum Processors

“…To illustrate the workload characteristics of a multi-core quantum computer, here we follow the methodology of [48], which is based on OpenQL [19]. We compile the 64-qubit Quantum Fourier Transform (QFT) algorithm [33] for an architecture of 8 cores with 8 qubits each, and then extract various characteristics of the intercore qubit traffic as depicted in Figure 4.…”

“…We compile the 64-qubit Quantum Fourier Transform (QFT) algorithm [33] for an architecture of 8 cores with 8 qubits each, and then extract various characteristics of the intercore qubit traffic as depicted in Figure 4. We next provide some insights based on the results of the QFT algorithm, even though the methodology can be used to profile the workload of any algorithm and analyze the differences among them [48].…”

Mapping quantum algorithms to multi-core quantum computing architectures

“…Inter-core communication: Similar to the single-chip case in which qubits need to be adjacent for interacting, qubits placed in different cores cannot directly perform a two-qubit gate. To do so, they have to make use of entanglement-based quantum communication protocols that require the generation of the so-called Bell pairs allowing to perform, for instance, remote CNOTs between distant qubits or to teleport quantum states from one core to another [27], [28]. This comes with an overhead of resources needed for creating and distributing entangled pairs.…”