Charge-Based Distortion Analysis of Nanoscale MOSFETs

Chicco, Francesco; Pezzotta, A.; Enz, Christian

doi:10.1109/tcsi.2018.2868387

Cited by 13 publications

(6 citation statements)

References 21 publications

(27 reference statements)

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“…The first one is a difference of the slope, n, and the second one is an underestimation of the drain current. The first discrepancy can be minimized by slightly adjusting the slope factor, n, to optimize the fit with the measurements [19], noticing that the variation of n vs. V D is small enough to be neglected. On the contrary, the current increase with V D has to be modeled by taking into account two major short-channel effects: the DIBL and the CLM.…”

Section: -Parameter Modelmentioning

confidence: 99%

“…The carrier velocity saturation effect models the limited increase of the velocity of the carriers when the longitudinal electric field (V DS /L) increases [9]. This effect has already been widely considered in the literature [12], [16], [17], [19]. In those published models, the carrier velocity saturation parameter is represented by ζ , which is defined as…”

Section: Modeling the Carrier Velocity Saturation Effect: ζmentioning

confidence: 99%

“…The 7-parameter model related to physical effects, as presented in the previous section, accurately describes the DC characteristics of the MOS transistors for long and short channel lengths. Indeed, as it has been already published in the literature, the main parameters of the model can be made scalable with L [12], [19], [21]. However, in a practical design application, designers often prefer to extract the model parameters for a fixed L in order to keep the model as simple as possible and reduce the set of parameters to be extracted.…”

Section: Consistency Of the Proposed Modelmentioning

confidence: 99%

See 2 more Smart Citations

Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge

et al. 2022

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This paper presents a 7-parameter analytical model of the MOS transistor based on the inversion charge targeted at the development of simplified analytical circuit design methodologies that take into account the physics of the MOS transistor. The proposed design-oriented model allows for the first time to describe both the main short-channel effects of advanced nanometric technologies and the dependence of the transistor drain current on the drain voltage, while the model remains valid for all bias regimes (from weak to strong inversion) and for all operating regions (linear and saturated). A simple procedure based on the device physics is proposed to estimate the transistor model parameters for a given technology. Furthermore, analytical expressions of the current derivatives are developed targeting different design scenarios. The accuracy of the proposed model is validated by direct comparison to silicon measurements of N-MOS transistors in 28 nm FD-SOI technology for channel width of 1 µm and channel lengths of 30 nm, 60 nm and 150 nm, and also to simulations performed with an industry-standard compact model. INDEX TERMSAnalytical MOSFET modeling, charge-based MOSFET model, design-oriented MOSFET model, inversion coefficient, nonlinear distortion, short-channel effects, 28 nm FD-SOI.

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Section: -Parameter Modelmentioning

confidence: 99%

Section: Modeling the Carrier Velocity Saturation Effect: ζmentioning

confidence: 99%

Section: Consistency Of the Proposed Modelmentioning

confidence: 99%

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Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge

et al. 2022

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“…ACM [2] and EKV [3] models are the basis of these IC-based or gm/ID-based design methodologies as they rely on the inversion charge of the MOS transistor. In addition, simplified versions of these models offers simple and suitable equations for circuit pre-conception [1], [4]- [7]. The simplest implementation of these models employs three parameters [8], [9]: the subthreshold slope factor, n, the specific current, IS0, and, the threshold voltage, VT. To comply with advanced nanometric technologies, more complex versions of these models have been developed to consider short-channel effects.…”

Section: Introductionmentioning

confidence: 99%

“…In the same way, another parameter named for ACM [10], or for EKV [11] was introduced to describe carrier velocity saturation. These models can be accurate enough especially for saturation and strong inversion regimes, allow for a better modeling of the saturation region and enable nonlinearity analysis [4]. However, these models fail to describe accurately the transition from the linear to the saturation region.…”

Section: Introductionmentioning

confidence: 99%

Design-oriented model for short-channel MOS transistors based on inversion charge

Pino-Monroy

Scheer

Bouchoucha

et al. 2023

2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)

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HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

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An analytical gm/ID‐based harmonic distortion prediction method for multistage operational amplifiers

Xie

Shi

2021

Circuit Theory & Apps

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SummaryAn analytical stage‐based harmonic distortion (HD) analysis method for multistage operational amplifiers (Op Amps) is developed in this work. This work contributes two fundamental methods that make the analytical HD prediction possible at the circuit level. Firstly, we propose that the traditionally used first order small‐signal transistor quantities gm (transconductance) and go (output conductance) in the gm/ID design methodology for bulk complementary metal‐oxide‐semiconductor (CMOS) technology can be extended to the higher order quantities gm(k) and go(k) ( ). With proper normalization, these quantities become neutral to the device dimensions and operation currents, hence can be precharacterized by sweeping simulations and used as lookup tables. Secondly, we further develop analytical nonlinearity expressions for a set of commonly used amplifier stages, represented as the functions of the nonlinearity parameters gm(k) and go(k) of the transistors that form a stage circuit. A combination of these two fundamental methods on hierarchical nonlinearity modeling enables us to apply the existing analytical HD estimation methods for the stage‐form macromodels to predict the circuit‐level HD behavior, overcoming the need of running repeated simulations under device resizing and rebiasing. The proposed harmonic distortion analysis method has been validated by application to real multistage amplifiers, achieving HD prediction results in excellent agreement to fully transistor‐level circuit simulation results but with substantial speedup.

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Charge-Based Distortion Analysis of Nanoscale MOSFETs

Cited by 13 publications

References 21 publications

Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge

Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge

Design-oriented model for short-channel MOS transistors based on inversion charge

An analytical gm/ID‐based harmonic distortion prediction method for multistage operational amplifiers

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