Charge-based fault simulation for CMOS network breaks

Abstract

We de ne a network break as a break fault in the p-network or in the n-network of a CMOS cell that breaks one or more transistor paths between the cell output and Vdd or GND. Previous work, mostly in the context of transistor stuck-open faults, studied test invalidation due to transient paths to Vdd or GND, and due to charge sharing. In this paper we show the importance of Miller feedthrough and feedback capacitances in network break test invalidation, which was ignored by previous work. We present a new fault simulation algorithm for network breaks, with the following novelties: First, the electrical charge coming from Miller and pn junction capacitances is computed using a transistor charge model 18]; this automatically handles the non-linear nature of transistor capacitances accurately, as opposed to assuming constant capacitance values as was done in previous work. Next, we use only six voltage levels for charge computations, which allows us to create look-up tables that dramatically reduce the computation time. Finally, the maximum voltage an internal node in an n-network can acquire is about three-fourths of the Vdd voltage (instead of Vdd as assumed by previous work), and similarly, a p-network node cannot discharge all the way down to the GND voltage.Using our simulator to analyze test sets for the ISCAS85 circuits, we found that the charge coming from Miller capacitances has a larger share in test invalidation than the charge from p-n junction capacitances. Our simulator spends less time for charge computations than it spends for transient path identi cation.

On modeling and testing of lithography related open faults in nano-CMOS circuits

“…We need the capability to detect these faults. Earlier, it was shown that such faults may be detected by inducing transition in the adjacent nets and thereby injecting charge into the floating nets [18].…”

Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

“…In such case, the analogue voltage can be pre-computed and saved in the corresponding cell test view. The proposed model, due to the lower LOP fault incidence in CMOS circuits [19][20][21], deliberately does not take into account charge sharing effects and transient paths to V DD or V SS effects [22].…”

Improving CMOS open defect coverage using hazard activated tests

“…One common defect mechanism that can cause large delay effects is floating nodes resulting from CMOS open defects. Small leakage currents in the defective devices, or in nominally turned off parallel paths, can sometimes slowly charge the node to the correct logic level [1], resulting in delay fault behavior from the opens. Figure 1 illustrates this for a simple NAND gate.…”