Charge-Based Modeling of Double-Gate and Nanowire Junctionless FETs Including Interface-Trapped Charges

Yesayan, Ashkhen; Jazaeri, Farzan; Sallèse, Jean-Michel

doi:10.1109/ted.2016.2521359

Cited by 32 publications

(17 citation statements)

References 16 publications

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“…This adds two additional Fermi-Dirac temperature dependencies f (E t,j ) (with E t,j a trap energy-level at position j in the bandgap), apart from the ionization probability f (E A ). The interface traps can be modeled as a discrete summation of traps, as explained in [43,44,45]. The temperature-dependent occupation of interface traps is important for a correct derivation of the subthreshold-swing formula, leading to hyperbolic temperature dependency of the slope factor (ignoring coupling effects between front and back gates), which will be discussed in more detail in Sec.…”

Section: Low-temperature Phenomenamentioning

confidence: 99%

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Beckers

Jazaeri

Bohuslavskyi

et al. 2019

Solid-State Electronics

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This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physicsbased cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.The birth of CMOS-compatible qubits in silicon [1,2,3,4] has rebooted the interest in cryogenic CMOS electronics for computing applications. Since the 1970s, MOSFET devices have been under investigation at cryogenic temperatures for use in custom applications, such as low-noise scientific equipment, spacecraft, power conversion etc. [5,6,7,8,9]. However, despite its many benefits for reaching high-performance and low-power computing [10], cryogenic cooling did not stay into practice for computing, abandoning the trend set by the ETA-10 liquid-nitrogen-cooled supercomputer [11].Nowadays, co-integrating qubits and CMOS circuits on the same substrate can greatly aid the development of scalable quantum computers featuring massive parallelism and error correction [12,13,14]. In this context, a silicon-on-insulator (SOI) platform is particularly attractive since the back gate provides additional control over the electron-spin qubit, trapped under the front gate of a SOI (nanowire) MOSFET[12,15,16]. To integrate the control circuits with quantum devices working at deep-cryogenic temperatures, regular SOI MOSFETs need to demonstrate reliable digital, analog and RF functionalities at such low temperatures. Using SOI cryogenic control electronics, the back gate can prove a useful tool to control the threshold voltage and hence the power consumption in circuits integrated close to the qubits [17], benefiting qubit coherence time by lowering generated noise. The main focus is on advanced ultra-thin body fully-depleted SOI (FDSOI) technology, e.g., the 28-nm node, to enable ultimate scalability of the resulting hybrid quantum-classical system [16,18].The 28-nm node, presently considered the ideal node for analog and RF applications at room temperature [19], has recently been tested for digital and analog functionality down to liquid-helium temperature (4.2 K) [17], and millikelvin temperature (20 mK) [20]. The improvement in RF characteristics has been verified down to liquid-nitrogen temperature (77 K) [21]. In addition to device c...

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Section: Low-temperature Phenomenamentioning

confidence: 99%

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Beckers

Jazaeri

Bohuslavskyi

et al. 2019

Solid-State Electronics

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“…where N is the number of interface traps, and is the Fermi-Dirac occupation probability of the trap energy level E t, j . The RHS of (13) is obtained by defining the trap potentials, ψ t, j (E t, j − E i )/q [46]- [48]. This leads to the flat-band voltage…”

Section: B Poisson-boltzmann Equationmentioning

confidence: 99%

Cryogenic MOS Transistor Model

Beckers

Jazaeri

Enz

2018

IEEE Trans. Electron Devices

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142

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This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell-Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation. Index Terms-Cryo-CMOS, cryogenic MOSFET, freezeout, incomplete ionization, interface traps, low temperature, MOS transistor, physical modeling. I. INTRODUCTION A DVANCED CMOS processes perform increasingly well from room temperature (RT) down to deep-cryogenic temperatures (<10 K) [1]-[3]. At these temperatures, the ideal switch with a steplike subthreshold slope comes within reach [4]. Furthermore, cryoelectronics [5]-[7] can provide an interface with superconducting devices on the quest for exascale supercomputing [8]. Ultimately, quantum-engineered devices controlled by cryo-CMOS circuits can bring new functionality to existing computing technologies [9], [10]. Large-scale integration of silicon spin qubits [11], [12] and cryo-CMOS control circuits is envisioned to take solid-state quantum computing to the next level [13]. Digital, analog, and RF CMOS circuits [14]-[16] are then required to operate at millikelvin temperatures for initialization, manipulation, and readout of the qubits, as well as error correction [17], [18].

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“…The structures like double gate, and Fin MOSFETs improve the short-channeleffects and the Ioff current behavior but difficulty in defining the boundary between the source and drain regions in doping profiles still exists [8]. The junctionless FET (JL-FET) that have no junction at the source-channel and channel-drain interfaces provides a solution to this problem but they show poor high-voltage characteristics [9]- [14][15], [16]- [21][22] [23]. Characteristics of high-voltage breakdown have been investigated in multigate structures [24] [25]and junctionless FETs [26].…”

Section: Introductionmentioning

confidence: 99%