Charge-Based Modeling of Radiation Damage in Symmetric Double-Gate MOSFETs

Jazaeri, Farzan; Zhang, Chunmin; Pezzotta, A.; Enz, Christian

doi:10.1109/jeds.2017.2772346

Cited by 29 publications

(23 citation statements)

References 43 publications

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“…In the extreme case of the presence of amphoteric interfacial traps [48], [49], then we have states at the same energy which can behave both as acceptors and donors. This is illustrated in Fig.…”

Section: A Linking the Interface States With A Uniform Behaviour Of mentioning

confidence: 99%

A Defects-Based Model on the Barrier Height Behavior in 3C-SiC-on-Si Schottky Barrier Diodes

Arvanitopoulos

Antoniou

Jennings

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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3C-Silicon Carbide (3C-SiC) Schottky Barrier Diodes on Silicon (Si) substrates (3C-SiC-on-Si) have been found to suffer of excessive sub-threshold current, despite the superior electrical properties of 3C-SiC. In turn, that is one of the factors deterring the commercialization of this technology. The forward Current-Voltage (I-V) characteristics in these devices carry considerable information about the material quality. In this context, an advanced Technology Computer Aided Design (TCAD) model is proposed and validated with measurements obtained from a fabricated and characterized Platinum/3C-SiCon-Si Schottky Barrier Diode with scope to shed light in the physical carrier transport mechanisms, the impact of traps and their characteristics on the actual device performance. The model includes defects originating from both the Schottky contact and the hetero-interface of 3C-SiC with Si, which allows the investigation of their impact on the magnification of the subthreshold current. Further, the simulation results and measured data allowed for the identification of additional distributions of interfacial states, the effect of which is linked to the observed nonuniformities of the Barrier Height value. A comprehensive characterization of the defects affecting the carrier transport mechanisms of the investigated 3C-SiC-on-Si power diode is thus achieved and the proposed TCAD model is able to accurately predict the device current both during forward and reverse bias conditions.

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Section: A Linking the Interface States With A Uniform Behaviour Of mentioning

confidence: 99%

A Defects-Based Model on the Barrier Height Behavior in 3C-SiC-on-Si Schottky Barrier Diodes

Arvanitopoulos

Antoniou

Jennings

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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“…Here, Q it is the interface-trap charge density per unit area. We consider a summation of discrete acceptor trap energy levels [46] (all donor states are occupied and neutral during turn ON in nMOS [27]). Each discrete trap energy level, E t, j , at position j in the bandgap has its particular N it, j -value assigned to it, where N it is the density-of-interface traps per unit area.…”

Section: B Poisson-boltzmann Equationmentioning

confidence: 99%

“…where N is the number of interface traps, and is the Fermi-Dirac occupation probability of the trap energy level E t, j . The RHS of (13) is obtained by defining the trap potentials, ψ t, j (E t, j − E i )/q [46]- [48]. This leads to the flat-band voltage…”

Section: B Poisson-boltzmann Equationmentioning

confidence: 99%

Cryogenic MOS Transistor Model

Beckers

Jazaeri

Enz

2018

IEEE Trans. Electron Devices

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143

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This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell-Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation. Index Terms-Cryo-CMOS, cryogenic MOSFET, freezeout, incomplete ionization, interface traps, low temperature, MOS transistor, physical modeling. I. INTRODUCTION A DVANCED CMOS processes perform increasingly well from room temperature (RT) down to deep-cryogenic temperatures (<10 K) [1]-[3]. At these temperatures, the ideal switch with a steplike subthreshold slope comes within reach [4]. Furthermore, cryoelectronics [5]-[7] can provide an interface with superconducting devices on the quest for exascale supercomputing [8]. Ultimately, quantum-engineered devices controlled by cryo-CMOS circuits can bring new functionality to existing computing technologies [9], [10]. Large-scale integration of silicon spin qubits [11], [12] and cryo-CMOS control circuits is envisioned to take solid-state quantum computing to the next level [13]. Digital, analog, and RF CMOS circuits [14]-[16] are then required to operate at millikelvin temperatures for initialization, manipulation, and readout of the qubits, as well as error correction [17], [18].

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“…Conversely, an acceptor-like trap with an energy level above the Fermi level is electrically neutral and will be negatively charged by trapping an electron if its energy is below the Fermi level [3] and [10]. Hence, Interface charge traps are amphoteric and their behavior as donors or acceptors depends on their energy in the band-gap [3], [8]. Fig.…”

Section: Gate Voltage Shift In Presence Of Interface Traps In Jlfetsmentioning

confidence: 99%

“…Modeling the effect of radiation on inversion mode MOS-FETs has already addressed in [8], but that model is not appropriate for junctionless devices. Influence of interface charge traps on biosensor junctionless devices was discussed in [3].…”

Section: Introductionmentioning

confidence: 99%

Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

Rassekh

Jazaeri

Fathipour

et al. 2019

IEEE Trans. Electron Devices

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In this paper, an analytical predictive model of interface charge traps in symmetric long channel doublegate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals, high-energy ionizing radiation or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperature from 77K to 400K. The validity of the approach is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation from deep depletion to accumulation and linear to saturation.

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Charge-Based Modeling of Radiation Damage in Symmetric Double-Gate MOSFETs

Cited by 29 publications

References 43 publications

A Defects-Based Model on the Barrier Height Behavior in 3C-SiC-on-Si Schottky Barrier Diodes

A Defects-Based Model on the Barrier Height Behavior in 3C-SiC-on-Si Schottky Barrier Diodes

Cryogenic MOS Transistor Model

Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

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