Charge-collection properties of irradiated depleted CMOS pixel test structures

Abstract

Edge-TCT and charge collection measurements with passive test structures made in LFoundry 150 nm CMOS process on p-type substrate with initial resistivity of over 3 kΩcm are presented. Measurements were made before and after irradiation with reactor neutrons up to 2·10 15 n eq /cm 2 . Two sets of devices were investigated: unthinned (700 µm) with substrate biased through the implant on top and thinned (200 µm) with processed and metallised backplane. Depletion depth was estimated with Edge-TCT and collected charge was measured with 90 Sr source using an external amplifier with 25 ns shaping time. Depletion depth at given bias voltage decreased with increasing neutron fluence but it was still larger than 70 µm at 250 V after the highest fluence. After irradiation much higher collected charge was measured with thinned detectors with processed backplane although the same depletion depth was observed with Edge-TCT. Most probable value of collected charge of over 5000 electrons was measured also after irradiation to 2·10 15 n eq /cm 2 . This is sufficient to ensure successful operation of these detectors at the outer layer of the pixel detector in the ATLAS experiment at the upgraded HL-LHC.

Charge collection in irradiated HV-CMOS detectors

“…The measured charge is less than the amount of charge deposited in depletion region estimated with Edge-TCT. A similar observation was made in [21], where the effect was attributed to biasing the detector from the top, causing charge 195 trapping in the low electric field region. This effect is smaller in segmented detectors or in detectors with a processed back plane.…”

“…For measurements of charge collection the sample was mounted between two collimators with 90 Sr source on one side and a scintillator coupled to a photomultiplier for triggering on the other side. The large pixel array was used achieved by biasing the detector from the back, but this approach requires back plane processing [21].…”

Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

“…High charge collection efficiency after radiation damage can be expected from a large charge collection electrode, together with the possibility of applying back-side reverse bias to achieve more uniform drift field. Measurement of a previous prototype shows that a depletion depth over 100 µm is achievable with such sensor design after particle fluence of 10 15 n eq /cm 2 [12], the expected NIEL radiation fluence for the ITk outer pixel layers. However, it may suffer from large detector capacitance, e.g.…”

“…The breakdown was measured at -280 V, an improvement over previous chip generation in the same technology [15], thanks to a new guard ring structure [16]. Such high breakdown voltage is likely to ensure a sufficient depletion after irradiation [7,12]. Noise and threshold distribution The noise performance and threshold distribution were studied by scanning an external injection voltage and recording the sensor response.…”

Time resolution and radiation tolerance of depleted CMOS sensors

“…Unthinned devices of 700 μm with topside biasing and thinned devices of 200 μm with backside biasing in the 150 nm HR/HV-CMOS node from LFoundry have been irradiated with neutrons for a range of fluences [24]. Measured results show that the depletion depth of unirradiated devices grows with the bias voltage very similarly in both cases, until the thinned devices reach full depletion.…”