2020
DOI: 10.1103/physrevapplied.14.024066
|View full text |Cite
|
Sign up to set email alerts
|

Charge Detection in an Array of CMOS Quantum Dots

Abstract: The recent development of arrays of quantum dots in semiconductor nanostructures highlights the progress of quantum devices toward a large scale. However, how to realize such arrays on a scalable platform such as silicon is still an open question. One of the main challenges lies in the detection of charges within the array. It is a prerequisite to initialize a desired charge state and read out spins through spin-to-charge conversion mechanisms. In this work, we use two methods based on either a single-lead cha… Show more

Help me understand this report
View preprint versions

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

2
59
0

Year Published

2020
2020
2022
2022

Publication Types

Select...
7

Relationship

3
4

Authors

Journals

citations
Cited by 67 publications
(61 citation statements)
references
References 37 publications
2
59
0
Order By: Relevance
“…We have also tested device stability, including charge noise (see “Methods” section) and reproducibility upon multiple thermal cycles from room temperature to base temperature (see Supplementary Table S2 ). In conjunction with complementary experiments in various other laboratories using similar LETI devices from the same fabrication run 14 , 18 , 34 , 35 , these results constitute key steps towards fault-tolerant quantum computing based on scalable, gate-defined quantum dots.…”
Section: Discussionmentioning
confidence: 63%
See 2 more Smart Citations
“…We have also tested device stability, including charge noise (see “Methods” section) and reproducibility upon multiple thermal cycles from room temperature to base temperature (see Supplementary Table S2 ). In conjunction with complementary experiments in various other laboratories using similar LETI devices from the same fabrication run 14 , 18 , 34 , 35 , these results constitute key steps towards fault-tolerant quantum computing based on scalable, gate-defined quantum dots.…”
Section: Discussionmentioning
confidence: 63%
“…S1 and refs. 17 , 18 ), we focus on a 2 × 2 quantum-dot array as the smallest two-dimensional unit cell in this architecture, that is, a device with two pairs of split-gate electrodes, labeled G i with corresponding control voltages V i . The device studied is similar to the one shown in Fig.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…This leads to the unique transfer and output characteristics, such as Coulomb blockade oscillation (CBO) and negative differential conductance (NDC), respectively [6][7][8][9][10][11][12][13][14][15]. For example, the precise control of the single-electron (or even single-spin) transport characteristics was demonstrated on various types of semiconductor QD-based DTJ and MTJ device schemes (e.g., room temperature observation of multiple CBO peaks from multiple quantum states in a Si single-QD device [10], simultaneous observation of both sharp CBO and NDC peaks from a Si-QD DTJ device [9][10][11][12][13][14], bias voltage-controlled precise modulation of energetic Coulomb blockade conditions in a Si single-QD transistor [8], high-fidelity q-bit processing in Si MQD [16][17][18][19] and GaAs MQD [20][21][22] devices). Such an extremely high precision of the single-charge manipulation could enable us to extend the SET application toward the broad area of the sensing metrology.…”
Section: Introductionmentioning
confidence: 99%
“…17 Although fabrication is advancing to complementary metal-oxide-semiconductor (CMOS) foundry-manufactured devices, 18,19 demonstrations on twodimensional quantum dot arrays have been limited to reaching singleelectron occupancy in up to three dots within a 2 Â 2 array. [20][21][22][23] Reaching simultaneously the single-charge regime with all quantum dots in a two-dimensional array fabricated using CMOS foundry compatible materials remains, thereby, an outstanding challenge.…”
mentioning
confidence: 99%