Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET

Nautiyal, Vivek; Singla, Gaurav; Singh, Satinderjit; Bohra, Fakhruddin Ali; Dasani, Jitendra; Gupta, Lovely; Dwivedi, Sagar

doi:10.1109/islped.2017.8009154

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…For example, [5] proposed WL control for read and write assists, [6] explains a negative bitline write assist, [7] explains a transient voltage collapse scheme for the write assist. [8] proposed an area efficient charge recycle integrated read and write assist scheme, while [9] does the comparison of different assist schemes for writeability improvement.…”

Section: Related Workmentioning

confidence: 99%

Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies

Nautiyal

Singla

Maiti

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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As CMOS technology scales with complex lithography, metal resistance increases. Specifically, at hightemperatures IR drop limits the performance and impacts the yield of CMOS circuits. For SRAM, bitline resistance limits the writeability of bitcells. This paper proposes a self-timed Write Aid circuit that helps the write driver by discharging the bitline from its opposite side. The use of this aid circuit at performance worst corner, improves write time by more than 40%. For a fixed wordline pulse width of 250ps, there is around 1.5 sigma write yield improvement at 0.765v operation. The proposed circuit has been implemented and Si validated in 7nm technology.

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Section: Related Workmentioning

confidence: 99%

Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies

Nautiyal

Singla

Maiti

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

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“…This restricts the minimal supply voltage (also known as V min ) scaling to achieve functional SRAM operation. One way to prevent such possible failures is to utilize circuit-assist techniques such as wordline underdrive (WLUD) [7] for read operations and supply voltage collapse (SVC) [8] and negative bitline (NBL) [9] during write operations. The aforementioned circuit-level assist solutions, on the other hand, necessitate a increment in power and area requirement, as well as a substantial increase in cycle time.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Yadav

Kondekar

Awadhiya

et al. 2022

Preprint

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In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14nm conventional FinFET to form NC-FinFET. Static and dynamic behaviour of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET-based SRAM, 6T-NCSRAM exhibits distinct behaviour during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

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Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by Inserted-Oxide FinFET Technology

Ding

Connelly

et al. 2019

IEEE Trans. Electron Devices

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Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET

Cited by 3 publications

References 9 publications

Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies

Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by Inserted-Oxide FinFET Technology

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