Charge recycling in MTCMOS circuits: concept and analysis

Pakbaznia,; Fallah,; Pedram,

doi:10.1109/dac.2006.229183

Cited by 17 publications

(25 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…From the discussion presented in [7], α depends on the ratio of the total capacitances in the virtual GND and virtual V DD rails. For the case of equal total capacitance on the virtual rails, we have α=0.5.…”

Section: Sizing and Placement Of The Charge-recycling Transistorsmentioning

confidence: 99%

“…From [7] we know that the first term in (5), ESR, depends only on the total capacitance ratio in the virtual ground and virtual V DD lines and does not depend on the charge recycling circuitry. Therefore, the problem of maximizing ESR row is equivalent to the problem of minimizing E cr-overhead or equivalently minimizing power overhead due to the charge-recycling transistors.…”

Section: Sizing and Placement Of The Charge-recycling Transistorsmentioning

confidence: 99%

“…None of these techniques propose any method to minimize the power consumption during the sleep-toactive and active-to-sleep mode transitions. Charge recycling technique has been recently proposed in order to reduce the energy consumption during mode transition of MTCMOS circuits [7]. It has been shown that by applying this technique, up to 46% of the switching energy due to mode transition can be saved [7].…”

Section: Introductionmentioning

confidence: 99%

“…The charge recycling transmission gate is turned on right before going from sleep to active and right after going from active to sleep. In [7] it has been discussed that during the active mode voltage values for nodes G and P are close to 0 and V DD , respectively. In the sleep mode, however, the reverse situation is valid and voltage values for Figure 1.…”

Section: Introductionmentioning

confidence: 99%

“…In the sleep mode, however, the reverse situation is valid and voltage values for Figure 1. The proposed charge recycling configuration in power gating structures [7].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Sizing and placement of charge recycling transistors in MTCMOS circuits

Pakbaznia

Fallah

Pedram

2007

2007 IEEE/ACM International Conference on Computer-Aided Design

View full text Add to dashboard Cite

-A downside of using Multi-Threshold CMOS (MTCMOS) technique for leakage reduction is the energy consumption during transitions between sleep and active modes. Previously, a charge recycling (CR) MTCMOS architecture was proposed to reduce the large amount of energy consumption that occurs during the mode transitions in powergated circuits. Considering the RC parasitics of the virtual ground and VDD lines, proper sizing and placement of chargerecycling transistors is key to achieving the maximum power saving. In this paper, we show that the sizing and placement problems of charge-recycling transistors in CR-MTCMOS can be formulated as a linear programming problem, and hence, can be efficiently solved using standard mathematical programming packages. The proposed sizing and placement techniques allow us to employ the CR-MTCMOS solution in large row-based standard cell layouts while achieving nearly the full potential of this power-gating architecture, i.e., we achieve 44% saving in switching energy due to the mode transition in CR-MTCMOS compared to standard MTCMOS.

show abstract

Section: Sizing and Placement Of The Charge-recycling Transistorsmentioning

confidence: 99%

Section: Sizing and Placement Of The Charge-recycling Transistorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…In the sleep mode, however, the reverse situation is valid and voltage values for Figure 1. The proposed charge recycling configuration in power gating structures [7].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations