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Abstract:Static power has become the most important factor in the fabrication of integrated circuits. Power gating techniques minimize leakage currents and help to develop ultra-low-power and high-performance digital circuits. In this paper, a power gating approach is proposed to minimize leakage for subnanometer technologies. Simulation results reveal that the proposed technique reduces maximum of 96% leakage power, 33% dynamic power, 49% drowsy power, and 16% energy as compared to conventional techniques. The proposed technique offers good leakage reduction, even under variation of different operating parameters.

Carbon Nanotube Field Effect Transistor (CNTFET) is one of the most promising candidates in the near future for digital design due to its better electrostatics and higher mobility characteristics. Parameters that determine the CNTFET performance are the number of tubes, pitch, diameter and oxide thickness. In this paper, a power gating design methodology to realise low power CNTFET digital circuits even under device parameter changes is presented. Investigation about the effect of different CNTFET parameters on dynamic and standby power is carried out. Simulation results reveal that the power gated circuits suppress a maximum of about 67% dynamic power and 59% standby power compared to conventional circuits.

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As the semiconductor devices are increases the very fast speed ,the size of the portable devices are shrinking down drastically. Hence which results demand for the long battery life for the electronic devices which we are using our day to day life. Memory in electronic device plays a critical role in order to processing the data as well as to store the data. But over the past decade the memory devices(SRAM and DRAM) suffers for the various factors due to leakage power, current etc. In this paper we are going to describe the a detailed study of various techniques to overcome the leakage factors affecting the SARAM devices. out of the several techniques differential leakage power technique has been one of the primary technique to overcome the leakage current in CMOS devices.