Charge Recycling in Power-Gated CMOS Circuits

Pakbaznia, Ehsan; Fallah, Farzan; Pedram, Massoud

doi:10.1109/tcad.2008.2003297

Cited by 28 publications

(13 citation statements)

References 27 publications

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“…The result is a much more aggressive reduction in voltage across the power gated logic but also has three advantages over single rail clamping [13]. Firstly the charge that is stored in the V V dd supply rail is recycled to charge up the V V ss supply rail in the sleep mode [17] achieving greater reduction in supply voltage in the same time frame at lower energy cost to single virtual rail clamping. This is shown in Fig.…”

Section: Wake-up Energy Cost Of Different Power Gating Approachesmentioning

confidence: 99%

Active Mode Subclock Power Gating

Mistry

Myers

Al-Hashimi

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-This paper presents a technique, called sub-clock power gating, for reducing leakage power during the active mode in low performance, energy constrained applications. The proposed technique achieves power reduction through two mechanisms: 1) power gating the combinational logic within the clock period (sub-clock) and 2) reducing the virtual supply to less than V th rather than shutting down completely as is the case in conventional power gating. To achieve this reduced voltage, a pair of NMOS and PMOS transistors are used at the head and foot of the power gated logic for symmetric virtual rail clamping of the power and ground supplies. The sub-clock power gating technique has been validated by incorporating it with an ARM Cortex-M0 microprocessor which was fabricated in a 65nm process. Two sets of experiments are done: the first experimentally validates the functionality of the proposed technique in the fabricated test chip and the second investigates the utility of the proposed technique in example applications. Measured results from the fabricated chip show 27% power saving during the active mode for an example wireless sensor node application when compared to the same microprocessor without sub-clock power gating.

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Section: Wake-up Energy Cost Of Different Power Gating Approachesmentioning

confidence: 99%

Active Mode Subclock Power Gating

Mistry

Myers

Al-Hashimi

et al. 2014

IEEE Trans. VLSI Syst.

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“…During the sleep period, when the sleep transistor is OFF, if the circuit block is large enough, then the VVSS node and all internal nodes in the circuit will charge to a high voltage level [8]. This is due to the higher leakage of the circuit block compared to that of the OFF sleep transistor, which eventually charges up all the internal nodes in the circuit block including the VVSS node.…”

Section: Wakeup Latency and Leakage: Sizing Ms1mentioning

confidence: 99%

Design and application of multimodal power gating structures

Pakbaznia

Pedram

2009

2009 10th International Symposium on Quality of Electronic Design

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-Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This paper presents a tri-modal switch cell that enables implementation of multimodal power gating, including active, data-retentive drowsy, and deep sleep modes. A circuit realization and design methodology are presented that allow one to take advantage of the ultra low leakage deep sleep mode, low leakage, but very fast wakeup, drowsy mode, and an additional low leakage data-retentive mode. Experimental results demonstrate the benefits of this new switch and corresponding power gating technique.

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“…MTCMOS circuits suffer from some drawbacks such as long wakeup latency, large amount of rush-thru current, and wasteful energy usage during mode transition [7]. In addition, due to data loss in the sleep mode, MTCMOS circuits usually use a data retention strategy to restore the pre-sleep state which they cannot afford to lose.…”

Section: Introductionmentioning

confidence: 99%

Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating

Pakbaznia

Pedram

2012

IEEE Trans. VLSI Syst.

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Abstract-A tri-modal Multi-Threshold CMOS (MTCMOS) switch design is presented. Similar to the conventional MTCMOS switches, the tri-modal switch comes in two flavors: header and footer. The trimodal switch provides three different power modes for the underlying circuit, active, drowsy, and sleep. The ability of data retention in the drowsy mode makes the proposed tri-modal switch an excellent candidate for implementing data-retentive power gating designs. We will see that three different low-power design schemes, namely data-retentive power gating, multi-drowsy mode structures, and on-chip dynamic voltage scaling, are implemented using the proposed tri-modal switch. We show that our proposal introduces superior low-power solutions across various circuit operating modes using a single circuitry.

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Charge Recycling in Power-Gated CMOS Circuits

Cited by 28 publications

References 27 publications

Active Mode Subclock Power Gating

Active Mode Subclock Power Gating

Design and application of multimodal power gating structures

Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating

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