The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs) with different gate dielectrics including single SiO 2 layer and double Si 3 N 4 /SiO 2 layer. Radiation-induced holes trapping is greater for single SiO 2 layer than for double Si 3 N 4 /SiO 2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO 2 at lower oxidation temperature. Gate bias during irradiation leads to different TH shift for different gate dielectrics. Single SiO 2 layer shows the worst negative TH at = 0 V, while double Si 3 N 4 /SiO 2 shows negative TH shift at = −5 V, positive TH shift at = 10 V, and negligible TH shift at = 0 V.