Charge-Transferred Presensing, Negatively Precharged Word-Line, and Temperature-Insensitive Power-Up Schemes for Low-Voltage DRAMs

Sim, Jaesung; Kwon, Kee-Won; Chun, Ki-Chul

doi:10.1109/jssc.2004.825224

Cited by 15 publications

(4 citation statements)

References 6 publications

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“…• We model the worst-case operating conditions with a temperature of 85°C. • We assume the junction leakage towards the body of the access transistors is the major charge leakage path of the cell [36,56,96,101,102,104]. • We tune other parameters (e.g., bitline capacitance and resistance) to the best of our ability so that the timing parameters derived from our model closely approximate real DDR4 datasheet values [38].…”

Section: Methodsmentioning

confidence: 99%

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

Luo¹,

Shahroodi²,

Hassan³

et al. 2020

Preprint

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DRAM is the prevalent main memory technology, but its long access latency can limit the performance of many workloads. Although prior works provide DRAM designs that reduce DRAM access latency, their reduced storage capacities hinder the performance of workloads that need large memory capacity. Because the capacity-latency trade-o is xed at design time, previous works cannot achieve maximum performance under very di erent and dynamic workload demands.This paper proposes Capacity-Latency-Recon gurable DRAM (CLR-DRAM), a new DRAM architecture that enables dynamic capacity-latency trade-o at low cost. CLR-DRAM allows dynamic recon guration of any DRAM row to switch between two operating modes: 1) max-capacity mode, where every DRAM cell operates individually to achieve approximately the same storage density as a density-optimized commodity DRAM chip and 2) high-performance mode, where two adjacent DRAM cells in a DRAM row and their sense ampli ers are coupled to operate as a single low-latency logical cell driven by a single logical sense ampli er.We implement CLR-DRAM by adding isolation transistors in each DRAM subarray. Our evaluations show that CLR-DRAM can improve system performance and DRAM energy consumption by 18.6% and 29.7% on average with four-core multiprogrammed workloads. We believe that CLR-DRAM opens new research directions for a system to adapt to the diverse and dynamically changing memory capacity and access latency demands of workloads.

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Section: Methodsmentioning

confidence: 99%

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

Luo¹,

Shahroodi²,

Hassan³

et al. 2020

Preprint

View full text Add to dashboard Cite

show abstract

“…T ODAY, there is an increased demand for the use of multiple voltage levels in various semiconductor circuits like nonvolatile memories [1]- [3], dynamic [4]- [6] and static [7], [8] random access memories, and low-power [9]- [11], and lowvoltage [12] circuits. High voltages, above the nominal technology voltage, and negative voltages are widely used in circuit operation along with the nominal power supply voltage .…”

Section: Introductionmentioning

confidence: 99%

A Stress-Relaxed Negative Voltage-Level Converter

Tsiatouhas

2007

IEEE Trans. Circuits Syst. II

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In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-m triple-well standard CMOS technology, using double-gate-oxidethickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of 3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported. Index Terms-Embedded negative voltage-level converter, level shifter, level conversion, MOS-device voltage stress relaxation.

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“…Memory circuits, such as dynamic random access memory (DRAM) arrays, have increased in complexity and density over time. To meet the technology trend, the memory circuits should adopt the low voltage and low power based scheme [1] [2].…”

Section: Introductionmentioning

confidence: 99%

A Sense Amplifier Scheme with Offset Cancellation for Giga-bit DRAM

Kang¹,

Hong²,

Chang³

et al. 2007

JSTS:Journal of Semiconductor Technology and Science

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To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about-0.3V to-0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip. Index Terms-DRAM, charge-transferred presensing (CTPS), negatively-driven sensing(NDS), free-level precharged bitline(FLPB), sense amplifier offset voltage, threshold voltage distribution.

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Charge-Transferred Presensing, Negatively Precharged Word-Line, and Temperature-Insensitive Power-Up Schemes for Low-Voltage DRAMs

Cited by 15 publications

References 6 publications

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

A Stress-Relaxed Negative Voltage-Level Converter

A Sense Amplifier Scheme with Offset Cancellation for Giga-bit DRAM

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