Charge Trapping in High-$k$Gate Stacks Due to the Bilayer Structure Itself

Jameson, John R.; Griffin, P.B.; Plummer, J. D.; Nishi, Yoshio

doi:10.1109/ted.2006.877700

Cited by 41 publications

(41 citation statements)

References 25 publications

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“…We conclude that the creation of new defects are gradually increasing and then slows, finally the upward exponential curve reaches saturation. (ii) This could also be explained with two simultaneous mechanisms together, namely, Maxwell-Wagner instability [29] and relaxation effect of the bilayers [31]. This metal-oxide high-j behaviour is contributed by dielectric polarization/relaxation and charge trapping/detrapping together.…”

Section: Resultsmentioning

confidence: 97%

“…When the gate bias is applied, the application of a gate bias will immediately produce a discontinuity in current density at the interface between the two layers, causing charge accumulation there until, in steady-state, the same current density flows through the both layers. If the gate bias is removed, a discontinuity in current density will again be produced, this time causing the charge to rush out of the gate stack [28,29].…”

Section: Introductionmentioning

confidence: 99%

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Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

Rahman¹,

Evangelou²,

Androulidakis³

2009

Microelectronics Reliability

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Section: Resultsmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

Rahman¹,

Evangelou²,

Androulidakis³

2009

Microelectronics Reliability

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“…Instabilities can be related to transition currents [12,13], dielectric relaxation current [14,15], dipole formation at the high-k/SiO 2 interface [16], Maxwell-Wagner instability in bilayer dielectric stacks [17] and trapping of electrons or holes on various types of traps [18,19]. Although some attempts were made to explain all these phenomena with a unified model, as due to the bilayer structure itself of the high-k dielectrics [20], it appears that the mechanisms affecting the instabilities depend on the specific high-k dielectric composition and fabrication conditions. In this paper we study the issue of flatband voltage instability in the case of Ta 2 O 5 .…”

Section: Introductionmentioning

confidence: 99%

HYSTERESIS-LIKE FLATBAND VOLTAGE INSTABILITIES IN Al/Ta2O5-SiO2/Si STRUCTURES AND THEIR CONNECTION WITH J-V CHARACTERISTICS

Novkovski¹,

Paskaleva²,

Atanassova³

2017

Contributions

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Flatband and current-voltage instabilities in unstressed Al/Ta 2 O 5 -SiO 2 /Si structures were studied in details. It has been found that, after an initial run left on fresh samples, both C-V and J-V characteristics exhibit repeatable patterns. Precisely repeatable counterclockwise hysteresis-like loop in C-V characteristics occurs, while no significant hysteretic behaviour is observed in static J-V characteristics. The reduced instability in J-V characteristics is explained by mutual compensation of two opposite effects owing to the presence of trapped positive charges on slow traps in the interfacial SiO 2 -like layer: (i) flatband voltage shift and (ii) lowering of Fowler-Nordheim tunnelling barrier for holes injected from the Si substrate. Correct determination of equivalent oxide thickness and fast interface state densities requires using the C-V curves obtained during the runs right, because progressive trapping on slow states occurs during the runs left. Value of the oxide charge is to be determined using the value of the flatband voltage obtained from the run left (after an initial run right), since it corresponds to the state of empty slow traps.

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“…However, this interpretation is limited to cases in which the displacement current dominates the whole conduction process. Additionally, this picture complicates even further because of the possible occurrence of the Maxwell-Wagner instability in dielectric stacks 25 .…”

mentioning

confidence: 99%

Multilevel recording in Bi-deficient Pt/BFO/SRO heterostructures based on ferroelectric resistive switching targeting high-density information storage in nonvolatile memories

Jiménez

Miranda

Tsurumaki‐Fukuchi

et al. 2013

Applied Physics Letters

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We demonstrate the feasibility of multilevel recording in Pt/Bi 1- FeO 3 /SrRuO 3 capacitors using the ferroelectric resistive switching phenomenon exhibited by the Pt/Bi 1- FeO 3 interface. A tunable population of up and down ferroelectric domains able to modulate the Schottky barrier height at the Pt/Bi 1- FeO 3 interface can be achieved by means of either a collection of SET/RESET voltages or current compliances. This programming scheme gives rise to well defined resistance states, which form the basis for a multilevel storage nonvolatile memory.

show abstract

Charge Trapping in High-$k$Gate Stacks Due to the Bilayer Structure Itself

Cited by 41 publications

References 25 publications

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

HYSTERESIS-LIKE FLATBAND VOLTAGE INSTABILITIES IN Al/Ta2O5-SiO2/Si STRUCTURES AND THEIR CONNECTION WITH J-V CHARACTERISTICS

Multilevel recording in Bi-deficient Pt/BFO/SRO heterostructures based on ferroelectric resistive switching targeting high-density information storage in nonvolatile memories

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