Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

Chien, Chien-Wei; Shen, Liang-Chi; Chang, Tao-Chih; Chang, Chin-Yao; Leu, Fang-Jun; Yang, Tsun-Hua; Ko, Cheng-Ta; Lee, Ching-Kuan; Shu, Chao-Kai; Lee, Yuan‐Chang; Hu, Shih−Cheng

doi:10.1109/ectc.2007.373814

Cited by 11 publications

(6 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In literature different techniques and approaches are proposed for die embedding in polymers [1,3,4]. In this paper, we use a so-called chip-first approach, meaning that first the die is transferred to the base wafer before processing the build-up around and on it.…”

Section: Die Embedding and Interconnectionsmentioning

confidence: 99%

“…Different techniques can be used for the patterning of the dielectric layers and opening the contacts. Patterning of the embedding polymer can be performed using laser drilling [3], plasma process or photolithography [1,2]. The main disadvantage of laser drilling is its locality; indeed the laser can only open one via at a time, this means that the laser has to move through the whole wafer to open all contacts.…”

Section: Die Embedding and Interconnectionsmentioning

confidence: 99%

“…Interconnectivity in the third dimension is realized by Through Silicon Via's (TSVs) in thin silicon and microbumps placed between the stacked layers. A different 3D approach allowing for chip stacking and chip-to-chip interconnectivity is the embedding and contact redistribution of thin dies in thin film interconnect layers [1][2][3][4]. Once embedded these structures can be stacked using, e.g., solder microbump technology.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

Iker

Tezcan

Teixeira

et al. 2007

2007 9th Electronics Packaging Technology Conference

View full text Add to dashboard Cite

This paper presents the process for the embedding of thin dies in a polymeric layer developed at IMEC. The different aspects of the fabrication process are described: the die thinning and singulation as well as the embedding itself including the redistribution of the thin die contacts. The embedding build-up is composed of photosensitive dielectric BCB and Copper plated metal films. Thinning, singulation and embedding of 15 µm thick Si dies is shown and electrical connection to pads having a pitch of 60 µm is demonstrated.

show abstract

Section: Die Embedding and Interconnectionsmentioning

confidence: 99%

Section: Die Embedding and Interconnectionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

Iker

Tezcan

Teixeira

et al. 2007

2007 9th Electronics Packaging Technology Conference

View full text Add to dashboard Cite

show abstract

“…IC packaging substrate as a special printed circuit board (PCB) for packaging semiconductor chip serves as a multifunctional carrier to protect chips from potential damage and provide rigid support, electrical response and power distribution (Chien et al , 2007; Dong et al , 2006; Dow et al , 2007; Ko et al , 2006). High-density IC packaging substrates are needed to meet the requirement of miniaturization and multifunctionalization for electric products (Hondo et al , 2013).…”

Section: Introductionmentioning

confidence: 99%

Improvement of plating uniformity for copper patterns of IC substrate with multi-physics coupling simulation

Xiang

Chen

Wang

et al. 2018

View full text Add to dashboard Cite

Purpose Optimized plating conditions, included proper designs of insulating shield (IS), auxiliary cathode (AC) and different patterns, contribute to the uniformity enhancement of copper deposition. Design/methodology/approach Plating experiments were implemented in vertical continuous plating (VCP) line for manufacturing in different conditions. Multiphysics coupling simulation was brought to investigate and predict the plating uniformity improvement of copper pattern. In addition, the numerical model was based on VCP to approach the practical application. Findings With disproportionate current distribution, different plating pattern design formed diverse copper thickness distribution (CTD). IS and AC improved plating uniformity of copper pattern because of current redistribution. Moreover, optimized plating condition for effectively depositing more uniformed plating copper layer in varied pattern designs were derived by simulation and verified by plating experiment. Originality/value The comparison between experiment and simulation revealed that multiphysics coupling is an efficient, reliable and of course environment-friendly tool to perform research on the uniformity of pattern plating in manufacturing.

show abstract

“…The specifications of the embedded LSI and SIRRIUS packages are shown in Table 1. While several organizations have been developing packaging technologies that have structures similar to that of SIRRIUS, [6][7][8][9] SIRRIUS features the ability to embed a highpin-count LSI with a comparably thin structure and sufficient reliability.…”

Section: Introductionmentioning

confidence: 99%

Warpage Mechanism of Thin Embedded LSI Packages

Nakashima

Kikuchi

Ohshima

et al. 2010

Transactions of The Japan Institute of Electronics Packaging

View full text Add to dashboard Cite

The warpage mechanism of a thin embedded LSI package with a thick Cu plate was investigated for various Cu plate thicknesses. The package warpage increased gradually as the Cu plate was made thinner. Even structures with a balanced Cu and resin layer configuration for the top and bottom portions of the embedded chip showed substantial warpage, especially in the chip region, that was greater than that for an unbalanced layer configuration. This indicates the existence of other warpage factors as well as unbalanced residual stress between the top and bottom of the chip. A 'Birth & Death' finite element method simulation showed that the thermal residual stresses induced by the coefficient of thermal expansion mismatch for the LSI chip and embedding resin were concentrated in the resin surrounding the lateral sides of the chip and that the stresses increased with decreasing Cu thickness. The release of these tensile stresses resulted in package warpage.

show abstract

Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

Cited by 11 publications

References 11 publications

3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

Improvement of plating uniformity for copper patterns of IC substrate with multi-physics coupling simulation

Warpage Mechanism of Thin Embedded LSI Packages

Contact Info

Product

Resources

About

Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

Cited by 11 publications

References 11 publications

3D Embedding and Interconnection of Ultra Thin (&#x226A; 20 &#x003BC;m) Silicon Dies

3D Embedding and Interconnection of Ultra Thin (&#x226A; 20 &#x003BC;m) Silicon Dies

Improvement of plating uniformity for copper patterns of IC substrate with multi-physics coupling simulation

Warpage Mechanism of Thin Embedded LSI Packages

Contact Info

Product

Resources

About

3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies