Chip Last Fan-Out Packaging for Millimeter Wave Application

Lu, Hsin-Chia; Wang, Yuanhong; Leou, Jeng-Long; Chan, Harrison; Chen, Scott

doi:10.1109/ectc.2016.197

Cited by 13 publications

(2 citation statements)

References 5 publications

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“…[14][15][16] Figure 2 shows a simplified image of the manufacturing process flows: The electrical connections between the die and package are implemented by direct RDL formation on the die pad in a die-first (facedown) process; [17,18] RDL formation is performed after CMP using a die-first (face-up) process; [19,20] and flip chip mounting to RDL is performed using solder bumps on the chip in an RDL-first process. [21,22] In this study, a die-first (face-down) process is selected as the manufacturing process because the corresponding mass production technology has already been established. Unlike other processes, the die-first (face-down) process does not require any components (e.g., Cu pillars, solder bumps) to connect to the RDL, which reduces the manufacturing cost.…”

Section: Issues and Solutions For Fowlpmentioning

confidence: 99%

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

Yamashita

Sekiguchi

2021

Transactions of The Japan Institute of Electronics Packaging

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Section: Issues and Solutions For Fowlpmentioning

confidence: 99%

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

Yamashita

Sekiguchi

2021

Transactions of The Japan Institute of Electronics Packaging

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“…For other chip-last or RDL-first potential applications, see Refs. [93][94][95][96][97][98][99][100][101][102][103].…”

Section: Chip-last or Rdl-first Processmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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A 77GHz Antenna-in-Package with Low-Cost Solution for Automotive Radar Applications

Hsieh

Jhong

et al. 2018

2018 IEEE 68th Electronic Components and Technology Conference (ECTC)

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Chip Last Fan-Out Packaging for Millimeter Wave Application

Cited by 13 publications

References 5 publications

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

A 77GHz Antenna-in-Package with Low-Cost Solution for Automotive Radar Applications

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