Chip Layout Optimization of SiC Power Modules Based on Multiobjective Electro-Thermal Design Strategy

Fukunaga, Shuhei; Funaki, Tsuyoshi

doi:10.1541/ieejjia.21006215

Cited by 8 publications

(2 citation statements)

References 25 publications

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“…Equation (2) considers the case of an ideal MOS capacitor where there is no work function difference between the metal and the semiconductor, and all doped impurities are ionized. Equation (2) shows that when the oxide charge Q ox changes due to gate oxide degradation, the depletion layer capacitances C dc and C dj are affected not only by the applied gate-source voltage v GS but also by the oxide charge Q ox . However, the oxide charge Q ox does not interact electrically with the semiconductor.…”

Section: Gate Oxide Degradation and Characteristics Fluctuation A The...mentioning

confidence: 99%

Operational Verification of Gate Drive Circuit With Condition Monitoring Function for Gate Oxide Degradation of SiC MOSFETs

Hayashi,

Wada

2024

IEEE Open J. Power Electron.

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This paper proposes a gate drive circuit with a condition monitoring function for detecting the gate oxide degradation in silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). Trapped charges in the gate oxide can cause fluctuations in the on-resistance and gate threshold voltages. These phenomena affect the long-term reliability of power conversion circuits. The proposed condition monitoring function detects the degradation of the gate oxide by measuring the input capacitance C iss versus the gate-source voltage v GS characteristics (C iss -v GS characteristics) of SiC MOSFETs implemented in power conversion circuits. Experiments on the proposed gate drive circuit were conducted using a 400 W-rated buck converter circuit in which a SiC MOSFET is implemented. The experimental results show that the gate drive circuit is capable of online measurement of C iss -v GS characteristics and gate drive at 20 kHz. The online measurement of the C iss -v GS characteristics corresponds to the offline measurement with a measurement instrument, indicating the effectiveness of the gate drive circuit.INDEX TERMS Condition monitoring, gate drive circuit, gate oxide, long-term reliability, SiC MOSFET.

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Section: Gate Oxide Degradation and Characteristics Fluctuation A The...mentioning

confidence: 99%

Operational Verification of Gate Drive Circuit With Condition Monitoring Function for Gate Oxide Degradation of SiC MOSFETs

Hayashi,

Wada

2024

IEEE Open J. Power Electron.

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“…Furthermore, stray inductance and capacitance result in oscillations in the switching waveforms, which are sources of noise [8]. Therefore, the development of bus bar and power module designs to optimize parasitic parameters has been investigated extensively [9], [10], [11], [12], [13]. Reference [14] presents a design procedure for an acceptable stray inductance in a high-speed switching circuit, considering the switching period, voltage, and current rating of the circuit.…”

Section: Introductionmentioning

confidence: 99%

Prediction Procedure of Parasitic Parameters Considering Laminated Bus Bar Geometries Based on Online Machine Learning

Shigetomi,

Wada

2023

IEEE Open J. Power Electron.

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The development of SiC and GaN power devices to achieve high-speed switching operations in power converter circuits is underway. The stray inductance caused by the bus bar geometries between DC capacitors and power devices influences high-speed switching circuits, such as surge voltages and switching losses. Therefore, the evaluation of the parasitic parameters is essential in designing power converter circuits. Currently, parasitic parameters that consider various bus bar geometries are calculated using finite element analysis (FEA) each time, which requires a large calculation time. This article proposes a prediction procedure for the parasitic parameters that easily and quickly consider complex bus bar geometries by performing online machine learning of FEA-based datasets. A laminated bus bar with two apertures to connect DC capacitors or power modules is analyzed, and the parasitic resistance, inductance, and capacitance are predicted. This article describes how large datasets can be obtained from multiple installments and perform online machine learning using XGBoost. To discuss the benefits of online machine learning, the prediction accuracy using test data in multiple machine learning models with different amounts of training data is compared. The mean relative error (MRE) between the predicted and analyzed values improves from 250% to 8% when parasitic parameters are predicted in the frequency range of 50 kHz to 100 MHz.INDEX TERMS Stray inductance, laminated bus bar, finite element analysis, machine learning, parasitic parameter.

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A Comparative Study on Optimization Algorithms in PowerSynth 2

Sanjabiasasi,

Al Razi,

Mantooth

et al. 2023

2023 IEEE Design Methodologies Conference (DMC)

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Chip Layout Optimization of SiC Power Modules Based on Multiobjective Electro-Thermal Design Strategy

Cited by 8 publications

References 25 publications

Operational Verification of Gate Drive Circuit With Condition Monitoring Function for Gate Oxide Degradation of SiC MOSFETs

Operational Verification of Gate Drive Circuit With Condition Monitoring Function for Gate Oxide Degradation of SiC MOSFETs

Prediction Procedure of Parasitic Parameters Considering Laminated Bus Bar Geometries Based on Online Machine Learning

A Comparative Study on Optimization Algorithms in PowerSynth 2

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