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Thermal characterization and modeling of power module is inevitable to take full advantages of power semiconductor device. Dynamic thermal modeling of power module, which is related to packaging structure and material property, is attracted attention for power electronics system design. The transient thermal resistance measurement standard, called static test method (JESD51-14 [1]), utilizes temperature dependency in I − V characteristics of power semiconductor device to estimate junction temperature. The dynamic gate threshold voltage shift of SiC MOSFET violates junction temperature estimation. This paper proposes accurate transient junction temperature estimation procedure for SiC MOSFET with advancing the static test method, and validates the temperature estimation with temperature sense diode embedded in SiC MOSFET. The proposed procedure enables to get accurate time response of T J for SiC MOSFET, which enables dynamic thermal modeling of power module with SiC MOSFET.

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Electro-thermal co-design of power modules is required to maximize the capabilities of promising power semiconductor devices. The chip layout on the substrate, which is restricted by the size of the power module substrate, determines the electrical and thermal characteristics of the power module. This paper proposes a chip layout optimization strategy for power modules based on a multiobjective electro-thermal design algorithm. The parasitic inductance and thermal resistance of the SiC power module are evaluated using the unified simulation model based on the multiphysics solver of the finite element method. The proposed multiobjective optimal design approach uses non-dominated sorting genetic algorithm II (NSGA-II) and the developed simulation model to obtain a Pareto front for the parasitic inductance and thermal resistance of the power module. Module samples with the obtained Pareto front parameters are experimentally characterized and validated with numerical simulation results.