Chip Multi-Processor Generator

Solomatnikov,; Firoozshahian,; Qadeer,; Shacham,; Kelley,; Asgar,; Wachs,; Hameed,; Horowitz,

doi:10.1109/dac.2007.375164

Cited by 4 publications

(5 citation statements)

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“…Our experiments use a CMP platform based on Tensilica's extensible RISC cores [2][39] [40]. This baseline implementation defines the gap we seek to bridge between general-purpose computing and ASIC efficiencies.…”

Section: Experimental Methodologymentioning

confidence: 99%

Understanding sources of inefficiency in general-purpose chips

HameedRehan

QadeerWajahat

WachsMegan

et al. 2010

SIGARCH Comput. Archit. News

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148

122

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Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance and energy efficiency. This paper explores the sources of these performance and energy overheads in general-purpose processing systems by quantifying the overheads of a 720p HD H.264 encoder running on a general-purpose CMP system. It then explores methods to eliminate these overheads by transforming the CPU into a specialized system for H.264 encoding. We evaluate the gains from customizations useful to broad classes of algorithms, such as SIMD units, as well as those specific to particular computation, such as customized storage and functional units.The ASIC is 500x more energy efficient than our original fourprocessor CMP. Broadly, applicable optimizations improve performance by 10x and energy by 7x. However, the very low energy costs of actual core ops (100s fJ in 90nm) mean that over 90% of the energy used in these solutions is still "overhead". Achieving ASIC-like performance and efficiency requires algorithm-specific optimizations. For each sub-algorithm of H.264, we create a large, specialized functional unit that is capable of executing 100s of operations per instruction. This improves performance and energy by an additional 25x and the final customized CMP matches an ASIC solution's performance within 3x of its energy and within comparable area.

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Section: Experimental Methodologymentioning

confidence: 99%

Understanding sources of inefficiency in general-purpose chips

HameedRehan

QadeerWajahat

WachsMegan

et al. 2010

SIGARCH Comput. Archit. News

Self Cite

148

122

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“…Large specialized units perform hundreds of operations for each data and instruction fetch, reducing energy waste of programmable cores by two orders of magnitude [20]. Significant research is now focusing on automatic generation of specialized units from high-level descriptions or templates in order to reduce design costs [27,13,31,19,26].…”

Section: Introductionmentioning

confidence: 99%

Convolution engine

Qadeer

Hameed

Shacham

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

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133

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This paper focuses on the trade-off between flexibility and efficiency in specialized computing. We observe that specialized units achieve most of their efficiency gains by tuning data storage and compute structures and their connectivity to the data-flow and datalocality patterns in the kernels. Hence, by identifying key data-flow patterns used in a domain, we can create efficient engines that can be programmed and reused across a wide range of applications.We present an example, the Convolution Engine (CE), specialized for the convolution-like data-flow that is common in computational photography, image processing, and video processing applications. CE achieves energy efficiency by capturing data reuse patterns, eliminating data transfer overheads, and enabling a large number of operations per memory access. We quantify the tradeoffs in efficiency and flexibility and demonstrate that CE is within a factor of 2-3x of the energy and area efficiency of custom units optimized for a single kernel. CE improves energy and area efficiency by 8-15x over a SIMD engine for most applications.

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“…In other words, if we start with a highly flexible design abstraction, and then automate the process of using con figuration information to produce an efficient implementation, we could produce chips with 10x lower NRE. This concept has been called a "Chip Generator" [3] [4].…”

Section: Introductionmentioning

confidence: 99%

Intermediate representations for controllers in chip generators

Kelley

Wachs

Danowitz

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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Creating parameterized "chip generators" has been proposed as one way to decrease chip NRE costs. While many approaches are available for creating or generating flexible data path elements, the design of flexible controllers is more prob lematic. The most common approach is to create a microcoded engine as the controller, which offers flexibility through pro grammable table-based lookup functions. This paper shows that after "programming" the hardware for the desired application, or applications, these flexible controller designs can be easily converted to efficient fixed (or less programmable) solutions using partial evaluation capabilities that are already present in most synthesis tools.

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Chip Multi-Processor Generator

Cited by 4 publications

References 0 publications

Understanding sources of inefficiency in general-purpose chips

Understanding sources of inefficiency in general-purpose chips

Convolution engine

Intermediate representations for controllers in chip generators

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