Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application

Kuechenmeister, Frank; Breuer, D.; Geisler, H.; Paul, J.; Shah, Chandravadan; Machani, Kashi Vishwanath; Kosgalwies, Sven; Agarwal, Rahul; Gao, Shan

doi:10.1109/eptc.2012.6507122

Cited by 13 publications

(2 citation statements)

References 3 publications

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“…The introduction of the ULK dielectric to the BEOL stack provided various electronic performance advantages, such as low RC delay, reduced power consumption, and low cross talk in interconnect technology; however, from a structural integrity perspective, the ULK dielectric is a porous organosilicate glass material and the intrinsic brittle mechanical nature of the ULK dielectric made the BEOL stack more vulnerable to external thermo-mechanical stress and chip-package interaction (CPI) became one of the biggest challenges in advanced packaging with advanced Si nodes using the ULK dielectric [1], [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

Cho

Gao

Choi

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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The need for high performance and multi-functional devices drove silicon manufacturers to introduce ultra-low dielectric constant (ULK) materials into the back-end-of-line (BEOL) of silicon manufacturing. This innovative technology resulted in performance boost and low RC delay as well as reduced power consumption and cross talk. Although ULK provides electrically improved performance compared to previous generation dielectric materials, it brought significant challenge since the ULK dielectric is a porous and brittle material with inferior material properties.At the same time, advanced packaging flip chip technology is migrating from conventional mass reflow (MR) bonding processing to thermo-compression bonding using non-conductive paste (TC-NCP) to enable higher I/O counts with a smaller form factor. The combination of these trends imposes a significant chip-package interaction (CPI) challenge. Thus CPI qualification of this technology is very crucial to provide the electronics industry the confidence to adopt this technology and prepare for high volume manufacturing.In this paper, Test vehicles with various CPI structures were used to assess the CPI risks of fine pitch flip chip technology with TC-NCP bonding process. To enable efficient routing at the substrate level, a bond-on-lead (BOL) substrate was used. JEDEC Standard CPI reliability test was performed and the data was reviewed electronically and mechanically at each read-out. The test results successfully demonstrate the robustness of GLOBALFOUNDRIES' 20-nm platform flip chip technology with Amkor Technology's TC-NCP bonding process.978-1-4799-8609-5/15/$31.00 ©2015 IEEE

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Section: Introductionmentioning

confidence: 99%

Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

Cho

Gao

Choi

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

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“…Therefore, CPI with Cu pillar flip chip packaging becomes very critical in leading edge technology node BEOL development and technology qualification. [1][2][3][4][5][6][7][8][9] In this paper, 20 nm CPI with fine pitch Cu pillar flip chip package is considered. A very systematic research on CPI test vehicle design, BEOL process optimization, ULK material properties characterization, packaging assembly process optimization, reliability tests, and failure analysis was conducted to develop and qualify 20 nm BEOL technology.…”

mentioning

confidence: 99%

Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond

Gao

Smith

Cho

et al. 2014

ECS J. Solid State Sci. Technol.

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Chip packaging interaction (CPI) has drawn great attention to advanced silicon technology nodes due to the introduction of Low-K (LK) and Ultra Low-K (ULK) materials in back end of line (BEOL) and Cu pillar in chip package interconnects. This paper summarizes GLOBALFOUNDRIES's activities in CPI studies for the 20 nm technology node, which includes CPI structure design, BEOL process characterization and optimization, assembly process optimization and reliability tests. The key issues and challenges were identified, analyzed, and overcome through a Design of Experiment (DOE) study in BEOL Q-time and reflow parameters in assembly process. It has been found that 1) BEOL ULK layer Q-time before SiCN capping is critical for moisture diffusion into BEOL materials, which affects both electrical performance and reliability; 2) Reflow temperature plays key role to control the package warpage to avoid non-wet issue. Package level reliability evaluation was performed and the results were reported. Through this study, it has been demonstrated that GLOBALFOUNDRIES's 20 nm technology successfully passed all CPI reliability tests. CPI challenges for future technology nodes and emerging packaging integration solutions are also discussed in the paper.

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Creep Parameters for Solder Interconnects by Nanoindentation Inverse-FEA Method

Li,

Taylor,

Arvin

2024

2024 IEEE 74th Electronic Components and Technology Conference (ECTC)

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Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application

Cited by 13 publications

References 3 publications

Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond

Creep Parameters for Solder Interconnects by Nanoindentation Inverse-FEA Method

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