Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond

Abstract

Chip packaging interaction (CPI) has drawn great attention to advanced silicon technology nodes due to the introduction of Low-K (LK) and Ultra Low-K (ULK) materials in back end of line (BEOL) and Cu pillar in chip package interconnects. This paper summarizes GLOBALFOUNDRIES's activities in CPI studies for the 20 nm technology node, which includes CPI structure design, BEOL process characterization and optimization, assembly process optimization and reliability tests. The key issues and challenges were identified, analyzed, and overcome through a Design of Experiment (DOE) study in BEOL Q-time and reflow parameters in assembly process. It has been found that 1) BEOL ULK layer Q-time before SiCN capping is critical for moisture diffusion into BEOL materials, which affects both electrical performance and reliability; 2) Reflow temperature plays key role to control the package warpage to avoid non-wet issue. Package level reliability evaluation was performed and the results were reported. Through this study, it has been demonstrated that GLOBALFOUNDRIES's 20 nm technology successfully passed all CPI reliability tests. CPI challenges for future technology nodes and emerging packaging integration solutions are also discussed in the paper.

Chip package interaction analysis for 20-nm technology with thermo-compression bonding with non-conductive paste

“…To address thermo-mechanical stress induced CPI risk, CPI test vehicle (TV) was developed with GLOBALFOUNDRIES 20-nm platform BEOL stack (1 low-k layer, 5 ULK layers, 2 TEOS layers, and final aluminum pad) and copper pillar (Cu pillar) technology [5]. The die size of the CPI TV was 9x8.45 mm 2 and a 14x14 mm 2 BOL substrate was used for CPI qualification.…”

An Investigation on the Most Likely Failure Locations in the BEoL Stack of a 20 nm Chip Due to Chip Package Interaction with the Use of Novel Semi-Elliptical Cracks

“…For example, Wang et al [14][15][16] used four-point bending tests to obtain the fracture toughness of the Cu/low-k interface and used the modified virtual crack closure technique (MVCCT) in a 3D model to analyze the fracture of the BEoL stack. Gao et al [17] used experimental methods to study the failure of a 6-layer BEoL stack due to high temperature and moisture. They demonstrated that the capacitance of the device rose significantly, and failure occurred in the BEoL layer when it was subjected to a temperature higher than 400 • C in a high-humidity environment.…”