Chip-Package Interaction Challenges for Large Die Applications

Wu, Zhuo-Jie; Carey, Charles; Donavan, Samantha; Hunt, Doug; Justison, Patrick; Anemikos, Theo; Cincotta, John; Gagnon, H.; Chacon, Oswaldo; Martel, Robert; Wassick, Thomas

doi:10.1109/ectc.2018.00104

Cited by 9 publications

(4 citation statements)

References 5 publications

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“…If the crack is blocked at one point, the energy will be released at an adjacent point. Wu et al 26 showed another useful perspective where the crack-stop location was important. They showed that as the crack propagates, it gains an energy release rate, creating more damage.…”

Section: Introductionmentioning

confidence: 99%

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Minimizing die fracture in 3DIC die integration

Bravo,

Morey-Chaisemartin,

Beisser

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Background: The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a thickness of 5 μm have been demonstrated. One significant barrier is the fragility of the thin dies, their overall thin form factor, and their impact on yield, reliability, and costs.Aim: We explore the current state of the art in the current crack stop and outline the shortcomings moving forward for stacked 3D integrated circuits (3DIC).Approach: Using a theoretical understanding of fracture mechanics and the new biomimetic concept adapted from nature, we show the implementation of the new crack stop insertions in the die frame for a next-generation 3DIC product. Results:The proposed crack stop can be easily inserted in the die frame with electronic design automation (EDA) tools using a Python interpreter and has the capability to arrest a crack near its initiation point. Conclusions:We show the feasibility of the implementation through EDA tools and outline the next step.

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Section: Introductionmentioning

confidence: 99%

“…If the crack is blocked at one point, the energy will be released at an adjacent point. Wu et al 26 . showed another useful perspective where the crack-stop location was important.…”

Section: Introductionmentioning

confidence: 99%

Minimizing die fracture in 3DIC die integration

Bravo,

Morey-Chaisemartin,

Beisser

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

View full text Add to dashboard Cite

show abstract

“…Over the past few years, demand has risen for electronic devices with increasing Input/Output (I/O) density and enhanced computational capabilities to support high-performance computing (HPC) applications such as AI (Artificial Intelligence) and machine learning. Flip Chip Ball Grid Array (FCBGA) packaging, 2.5D/3D heterogeneous integration packages, and Fan-Out Chip on Substrate (FOCoS) are the mainstay of such devices [ 1 , 2 , 3 , 4 ]. FCBGA (see Figure 1 a) is particularly common in telecom, workstation, and computer applications due to its superior bandwidth and electrical performance.…”

Section: Introductionmentioning

confidence: 99%

Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions

et al. 2023

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Flip Chip Ball Grid Array (FCBGA) packages, together with many other heterogeneous integration packages, are widely used in high I/O (Input/Output) density and high-performance computing applications. The thermal dissipation efficiency of such packages is often improved through the use of an external heat sink. However, the heat sink increases the solder joint inelastic strain energy density, and thus reduces the board-level thermal cycling test reliability. The present study constructs a three-dimensional (3D) numerical model to investigate the solder joint reliability of a lidless on-board FCBGA package with heat sink effects under thermal cycling testing, in accordance with JEDEC standard test condition G (a thermal range of −40 to 125 °C and a dwell/ramp time of 15/15 min). The validity of the numerical model is confirmed by comparing the predicted warpage of the FCBGA package with the experimental measurements obtained using a shadow moiré system. The effects of the heat sink and loading distance on the solder joint reliability performance are then examined. It is shown that the addition of the heat sink and a longer loading distance increase the solder ball creep strain energy density (CSED) and degrade the package reliability performance accordingly.

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“…The reliability of a WLCSP needs to be thoroughly assessed and understood before implementing this assembly technology for production. It is well known that the chippackage interaction (CPI) in flip chip can result in reliability fails such as white bump, die corner crack and delamination, and solder fatigue [4][5][6][7]. In WLCSP, chip is directly attached to PCB which has drastically dissimilar material properties compared to chip.…”

Section: Introductionmentioning

confidence: 99%

Understanding and Improving Reliability for Wafer Level Chip Scale Package: A Study Based on 45nm RFSOI Technology for 5G Applications

Zhang

Malinowski

2020

IEEE J. Electron Devices Soc.

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Wafer level chip scale package (WLCSP) is true chip scale package with low cost by eliminating package substrate. The direct chip-to-board attach through solder joints provides low interconnect inductance and resistance, as well as improved thermal performance. These properties make WLCSP a packaging format well suited for 5G radio frequency (RF) applications where minimized package size and parasitics as well as thermal performance are critical. Due to the dissimilar properties between chip and board, the reliability of WLCSP can be challenging. This paper reports a reliability study of WLCSP using 45nm RFSOI technology for 5G RF applications. Dedicated test chips and boards were designed and used for board level reliability tests. The test vehicles passed bHAST and drop test, whereas it is found that temperature cycling on board (TCoB) is challenging for solder joint reliability in some cases. Thorough tests were carried out based on Kelvin test on specially designed individual bump and bump pair structures and developed fail criterion. Finite element modeling was adopted to simulate the reliability performance in different configurations. The impact on reliability performance from bump depopulation, die thickness, bump size, UBM to board pad alignment, and board wiring trace were thoroughly investigated. Based on comprehensive testing and deep understanding of the failure mechanisms, design optimizations for chip, board and interconnect were implemented. WLCSP reliability was significantly improved.

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Chip-Package Interaction Challenges for Large Die Applications

Cited by 9 publications

References 5 publications

Minimizing die fracture in 3DIC die integration

Minimizing die fracture in 3DIC die integration

Reliability Evaluation of Board-Level Flip-Chip Package under Coupled Mechanical Compression and Thermal Cycling Test Conditions

Understanding and Improving Reliability for Wafer Level Chip Scale Package: A Study Based on 45nm RFSOI Technology for 5G Applications

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