Chip-to-chip interconnect integration technologies

Zia, Muneeb; Zhang, Chaoqi; Yang, Hyun Suk; Zheng, Li; Bakir, Muhannad S.

doi:10.1587/elex.13.20162001

Cited by 7 publications

(2 citation statements)

References 28 publications

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“…With the advent of through-wafer-via or through-silicon via (TSV) technology, [1][2][3][4][5] an enormous enhancement of computing performance at the edge terminal is being made possible owing to the several order increase in the number of I/Os with smaller form-factor and reduced wire-length. TSV is the key element to realize the various forms of threedimensional (3D) heterogeneous integration such as chip-to-chip, [6][7][8] chip-to-wafer, [9][10][11] wafer-to-wafer, [12][13][14] etc. The schematic cross-sectional view shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

Murugesan¹,

Mori²,

Bea³

et al. 2020

Jpn. J. Appl. Phys.

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A feasibility study has been carried out to find an alternative method to the laborious cum expensive physical vapor deposition (PVD)/atomic layer deposition for the deposition of barrier and seed metal layers inside the deep Si trenches with aspect ratio (AR) greater than 10, by using low-cost, highly-scalable, CMOS-compatible electroless (EL) plating method to plate Ni as (barrier cum) seed layer for the fabrication of sub-μm as well as 10 μm width copper through-silicon-vias (Cu-TSVs). Micro-structural data revealed that both sub-μm and 10 μm width TSVs with AR ranging from 12 to 17 were completely filled with Cu by using EL-Ni as a seed layer. Further, both scanning electron microscope and energy dispersive X-ray analyzes data confirms the conformal formation of EL-Ni all through TSV sidewall and TSV bottom, which is otherwise difficult to realize by the even sophisticated PVD tool. Therefore, the EL plating method appears to be a highly promising method for the conformal formation of barrier/seed layers inside the high AR TSVs for future three-dimensional integration and packaging applications.

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Section: Introductionmentioning

confidence: 99%

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

Murugesan¹,

Mori²,

Bea³

et al. 2020

Jpn. J. Appl. Phys.

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show abstract

“…As the number of cores increasing, the gap tends to be widened. Traditional memory interconnection such as bus-based architecture cannot meet the performance requirement of future memory access system [1,2]. In order to further improve the memory system performance in post-moore law period, memorycentric network (MCN) has been proposed [3,4,5].…”

Section: Introductionmentioning

confidence: 99%

ALPHA: A hybrid topology for memory-centric network

et al. 2019

IEICE Electron. Express

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Memory system, as the basic constituent of the computing system, has a inevitable impact on the system performance. Traditional bus-based memory access system cannot fulfill the performance requirement of the future high-performance computing system due to its limitation on energy-efficiency. Memory-centric network (MCN) is considered as a promising candidate for future system interconnect. To improve the energyefficiency of memory access system by utilizing MCN, the topology of MCN needs to be carefully designed, as interconnection links take a huge part of power consumption. In this letter, we propose a new memory network topology named ALPHA. ALPHA is a 2-D topology. As ALPHA employs different types of interconnection links in the X-dimension and the Ydimension, respectively, it can maintain high throughput while using fewer links. Besides we redesign the switch of HMC for its implementation in ALPHA. We make a comparison between ALPHA and four popular topologies. The simulation results show that ALPHA greatly increases throughput and decreases latency.

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A novel phased-shifted Bragg grating for Bloch surface waves

Wei

Xiao

2018

2018 Asia Communications and Photonics Conference (ACP)

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Chip-to-chip interconnect integration technologies

Cited by 7 publications

References 28 publications

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

ALPHA: A hybrid topology for memory-centric network

A novel phased-shifted Bragg grating for Bloch surface waves

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