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Cited by 12 publications
References 11 publications
Improvements in computing performance and efficiency recently opened up opportunities [1] in artificial intelligence (AI), represented by the seminal work of Alex Krizhevsky et al. [2] in 2012 where graphic processing units (GPUs) combined with big data excelled on an image classification task (top-5 error rate of 15.3% achieved by artificial neural networks vs 26.2% from the runner-up algorithms). This achievement reignited the attention for deep neural networks dating back to the 1980s, [3,4] in particular for convolutional neural networks (CNNs). Further efforts to optimize computing hardware are being actively pursued, such as using fieldprogrammable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), [5,6] including the tensor processing units (TPUs) [7,8] developed by Google and system on a chip (SoC)-scale AI accelerators used in mobile phones. This recent progress in computing hardware is still bound to CMOS technology, where the von Neumann bottleneck [9] limits speed and power efficiency. In-memory analog computing based on Ohm's and Kirchhoff 's laws, [10][11][12] utilizing nonvolatile memories (NVMs), such as resistive random access memory (RRAM), [13][14][15] phase-change memory (PCM), [16,17] and flash memory, [18][19][20][21] is a promising route to eliminate the von Neumann bottleneck and implement neuromorphic computing circuits for future AI systems. [22][23][24][25][26] Here we present a dynamical compact model for three-terminal silicon-oxide-nitride-oxide-silicon (SONOS) synaptic circuit elements. Three-terminal memory devices such as floating gate (FG) or SONOS flash memories have a long history for manufacturable data storage applications, but their compact models have relied on static metal-oxide-semiconductor field-effect transistor (MOSFET) behavior. [27][28][29] Moreover, a significant number of three-terminal synaptic devices are now being reported with various material systems, [30][31][32] but most publications describe experimental characterization without supplying a compact model, [33] so there exists a significant gap between the device community and circuit designers. Our work addresses this gap by constructing a well-posed compact model for three-terminal synaptic circuit elements, [34][35][36] beginning with the technologically mature SONOS device, which is a staple for NAND flash memory products. [37][38][39][40] In this work, we utilized technology computeraided design (TCAD) physics-based calculations within Synopsys Sentaurus to simulate the physics of a device and identified a key state variable Q M , the amount of charge in the SONOS trap layer, to guide us in constructing a compact model. Subsequently, we validated the model through a circuit simulation using Cadence Spectre to compare with the experimentally measured behavior of source-drain current after applying a wide range of voltage pulse amplitudes on the gate of a SONOS device. The use of both physics-based simulations and experimental data to identify the state variables and calibrate the ...
Improvements in computing performance and efficiency recently opened up opportunities [1] in artificial intelligence (AI), represented by the seminal work of Alex Krizhevsky et al. [2] in 2012 where graphic processing units (GPUs) combined with big data excelled on an image classification task (top-5 error rate of 15.3% achieved by artificial neural networks vs 26.2% from the runner-up algorithms). This achievement reignited the attention for deep neural networks dating back to the 1980s, [3,4] in particular for convolutional neural networks (CNNs). Further efforts to optimize computing hardware are being actively pursued, such as using fieldprogrammable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), [5,6] including the tensor processing units (TPUs) [7,8] developed by Google and system on a chip (SoC)-scale AI accelerators used in mobile phones. This recent progress in computing hardware is still bound to CMOS technology, where the von Neumann bottleneck [9] limits speed and power efficiency. In-memory analog computing based on Ohm's and Kirchhoff 's laws, [10][11][12] utilizing nonvolatile memories (NVMs), such as resistive random access memory (RRAM), [13][14][15] phase-change memory (PCM), [16,17] and flash memory, [18][19][20][21] is a promising route to eliminate the von Neumann bottleneck and implement neuromorphic computing circuits for future AI systems. [22][23][24][25][26] Here we present a dynamical compact model for three-terminal silicon-oxide-nitride-oxide-silicon (SONOS) synaptic circuit elements. Three-terminal memory devices such as floating gate (FG) or SONOS flash memories have a long history for manufacturable data storage applications, but their compact models have relied on static metal-oxide-semiconductor field-effect transistor (MOSFET) behavior. [27][28][29] Moreover, a significant number of three-terminal synaptic devices are now being reported with various material systems, [30][31][32] but most publications describe experimental characterization without supplying a compact model, [33] so there exists a significant gap between the device community and circuit designers. Our work addresses this gap by constructing a well-posed compact model for three-terminal synaptic circuit elements, [34][35][36] beginning with the technologically mature SONOS device, which is a staple for NAND flash memory products. [37][38][39][40] In this work, we utilized technology computeraided design (TCAD) physics-based calculations within Synopsys Sentaurus to simulate the physics of a device and identified a key state variable Q M , the amount of charge in the SONOS trap layer, to guide us in constructing a compact model. Subsequently, we validated the model through a circuit simulation using Cadence Spectre to compare with the experimentally measured behavior of source-drain current after applying a wide range of voltage pulse amplitudes on the gate of a SONOS device. The use of both physics-based simulations and experimental data to identify the state variables and calibrate the ...
AI Makes Crypto Evolve
No abstract
Since the inception of encrypted messages thousands of years ago, mathematicians and scientists have continued to improve encryption algorithms in order to create more secure means of communication. These improvements came by means of more complex encryption algorithms that have stronger security features such as larger keys and trusted third parties. While many new processors can handle these more complex encryption algorithms, IoT devices on the edge often struggle to keep up with resource intensive encryption standards. In order to meet this demand for lightweight, secure encryption on the edge, this paper proposes a novel solution, called the High and Low (HaLo) method, that generates Physical Unclonable Function (PUF) signatures based on process variations within flash memory. These PUF signatures can be used to uniquely identify and authenticate remote sensors, and help ensure that messages being sent from remote sensors are encrypted adequately without requiring computationally expensive methods. The HaLo method consumes 20x less power than conventional authentication schemes commonly used with IoT devices, it has an average latency of only 39ms for 512 bit signature generation, and the average error rate is below 0.06%. Due to its low latency, low error rate, and high power efficiency, the HaLo method can progress the field of IoT encryption standards by accurately and efficiently authenticating remote sensors without sacrificing encryption integrity.
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