Circuit activity based logic synthesis for low power reliable operations

Abstract

Circuit activity or the average number of transitions at a node is a measure of power dissipation in digital CMOS circuits. Circuit activity is also related to electromigration, and hot electron effects which can degrade reliability. In this paper, we address the problem of both finite state machine and combinational logic synthesis to minimize the average number of transitions at CMOS circuit nodes for battery-operated, low-power operations and increased reliability, while minimizing area at the same time. Logic can be optimally synthesized suited for different applications requiring different types of inputs. Results have been obtained for a wide range of MCNC benchmark examples.

Power minimization in IC design

“…These techniques can be modified to minimize the power dissipation. One approach is to minimize the switching activity on the present state lines of the machine by giving minimum-distance (ideally uni-distance) codes to states with high transition frequencies to one another [124]. In [49], a fully implicit encoding algorithm for reducing the average number of bit changes per state transition is presented.…”

“…Extraction based on algebraic division (using cube-free primary divisors or kernels) has proven to be very successful in creating an area-optimized multi-level Boolean network [13] and [119]. The kernel extraction procedure is modified in [124] to generate multi-level circuits with low power consumption. The main idea is to calculate the power savings factor for each candidate kernel based on how its extraction will affect the loading on its input lines and the amount of logic sharing.…”

Logic synthesis for reliability: an early start to controlling electromigration and hot-carrier effects

“…Recently, power dissipation during the logic synthesis process has been coilsidered [3]. However, there exists no such tool which consider reliability early during the design process.…”

Finite state machine decomposition for low power

“…This problem has received some attention recently. Several techniques for state assignment have been presented which aim at reducing the average switching activity of the present state lines, and consequently of the internal nodes in the combinational logic block (see for example [12]). Retiming has also been tailored so that the distribution of the registers within the logic block minimizes the total amount of glitching in the sequential circuit [9].…”