Logic synthesis for reliability: an early start to controlling electromigration and hot-carrier effects

Roy, Kaushik; Prasad, Sharat C.

doi:10.1109/24.387379

Cited by 14 publications

(5 citation statements)

References 9 publications

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“…Susceptibility to hot-carrier effects has also been reduced by minimizing the switching activity at the outputs of the logic gates in Roy and Prasad [1994].…”

Section: Related Researchmentioning

confidence: 99%

Introspection

Karri¹,

Iyer

2001

ACM Trans. Des. Autom. Electron. Syst.

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We report a register transfer level technique for concurrent error detection and diagnosis in data dominated designs called Introspection. Introspection uses idle computation cyles in the data path and idle data transfer cycles in the interconnection network in a synergistic fashion for concurrent error detection and diagnosis (CEDD). The resulting on-chip fault latencies are one ten-thousandth (10 −4 ) of previously reported system level concurrent error detection and diagnosis latencies. The associated area overhead and performance penalty are negligible. We derive a cost function that considers introspection constraints such as (i) executing an operation on three disjoint function units for diagnosis and (ii) promoting function units to participate in at least one CEDD operation. We formulate integration of introspection constraints into the operation-to-operator binding phase of high-level synthesis as a weighted bipartite matching problem. The effectiveness of introspection and its implementation are illustrated on numerous industrial strength benchmarks.

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“…Susceptibility to hot-carrier effects has also been reduced by minimizing the switching activity at the outputs of the logic gates in Roy and Prasad [1994].…”

Section: Related Researchmentioning

confidence: 99%

Introspection

Karri¹,

Iyer

2001

ACM Trans. Des. Autom. Electron. Syst.

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“…One category includes such techniques as transistor reordering and resizing [7], technology mapping [5], and technology-independent factorization [22] to minimize the maximum hot-carrier degradation effects among all transistors in the circuit. That is, each transistor in the circuit is labeled with a relative degradation factor and the optimization goal is to minimize the maximum of these factors.…”

Section: Delay-constrained Reliability Optimizationmentioning

confidence: 99%

Fast postplacement optimization using functional symmetries

Chang

Hsiao

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The timing-convergence problem arises because estimations made during logic synthesis may not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear-time algorithm is proposed to detect functional symmetries in the Boolean network which are then used as the basis for rewiring. Integration with an existing gate-sizing algorithm further proves the effectiveness of our technique. Three applications are demonstrated: delay, power, and reliability optimization.

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“…Tools such as RELIC [8], SPIDER [7], CREST [11] and BERT-EM [2] perform transient analyses and determines current density and electromigration failure for each element. CAD techniques for hot-carrier reliability h a v e also been developed [6,13].…”

Section: Introductionmentioning

confidence: 99%

Electromigration reliability enhancement via bus activity distribution

Dasgupta

Karri

1996

Proceedings of the 33rd Annual Conference on Design Automation Conference - DAC '96

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Electromigration induced d e gradation in integrated circuits has been accelerated b y c ontinuous scaling of device dimensions. We present a methodology for synthesizing high-reliability and low-energy microarchitectures at the RT level by judiciously binding and scheduling the data transfers of a control data ow graph(CDFG) representation of the application onto the buses in the microarchitecture. The proposed method a c c ounts for correlations between data transfers and the constraints on the number of buses, area and delay.

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Logic synthesis for reliability: an early start to controlling electromigration and hot-carrier effects

Cited by 14 publications

References 9 publications

Introspection

Introspection

Fast postplacement optimization using functional symmetries

Electromigration reliability enhancement via bus activity distribution

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