Circuit Aware Approximate System Design With Case Studies in Image Processing and Neural Networks

Ayhan, Tuba; Altun, Mustafa

doi:10.1109/access.2018.2889110

Cited by 7 publications

(4 citation statements)

References 25 publications

(26 reference statements)

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“…2 Identify application elements, i.e., variables/computations that can be approximated (Code snippet: three compute operations and related loads). 3 Identify potential approximation configurations such that their assignments to application elements meet the application's error tolerance requirements. 4 Choose the right approximation configuration to maximize any specified execution metrics such as performance, energy efficiency, or power.…”

Section: Hw-cognizant Approximation Tuningmentioning

confidence: 99%

“…In SHASTA, SCA is capable of fine-grained spatio-temporally diverse approximation by allowing the following: 1 It can uniquely control each dynamic approximation execution's computation time individually, 2 It allows same compute units to be used for both accurate and entire range of (timing) approximate compute, thus allowing fine-grained per-operation control without significant overheads, and 3 The computation time can be chosen from multiple discrete levels, every clock cycle, for every operation, depending on the amount of approximation the operation can endure.…”

Section: Design Of Approximation Hardware 41 Compute Timing Approximmentioning

confidence: 99%

“…Such solutions are sub-optimal, since they do not target a specific execution metric (e.g., performance or energy) and ignore features of the execution hardware. While some application-centric systems have analyzed the system as a whole to perform approximation tuning [1,3,12,28,30], these proposals are either not designed with a general purpose system in mind or they are unsuited to fine granularity and spatio-temporal diversity in approximation.…”

Section: Approximation At the Application Level Approximation Proposmentioning

confidence: 99%

“…All types of approximation can be supported the tuning mechanism as long as each type clearly identifies how the approximation mechanism varies for each "level" of approximation. Pseudocode for the tuning mechanism atop an application is shown in Listing 2 and features of the mechanism are discussed below.1 Each tuning epoch involves tuning the application's approximation configuration with some characteristic sample input.2 The tuning epoch starts with capturing the golden accurate application output, i.e., with no approximation, and its corresponding golden hardware execution metric (e.g., IPC/energy, using hardware/software counters) 3. The tuning mechanism will then run multiple "outer-loop" iterations of the application, each performing a set of "inner-loop" iterations.4 Every "outer-loop" iteration of the tuning mechanism starts with a current approximation configuration.…”

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confidence: 99%

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Shasta

Ravi

Miguel

Lipasti

2020

ACM Trans. Archit. Code Optim.

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Madison, Electrical and Computer Engineering A key requirement for efficient general purpose approximate computing is an amalgamation of flexible hardware design and intelligent application tuning, which together can leverage the appropriate amount of approximation that the applications engender and reap the best efficiency gains from them. To achieve this, we have identified three important features to build better general-purpose cross-layer approximation systems: 1 individual per-operation ("spatio-temporally fine-grained") approximation, 2 hardware-cognizant application tuning for approximation, 3 systemwide approximation-synergy. We build an efficient general purpose approximation system called SHASTA: Synergic HW-SW Architecture for Spatio-Temporal Approximation, to achieve these goals. 1 First, in terms of hardware, SHASTA approximates both compute and memory-SHASTA proposes (a) a form of timing approximation called Slackcontrol Approximation, which controls the computation timing of each approximation operation and (b) a Dynamic Pre-L1 Load Approximation mechanism to approximate loads prior to cache access. These hardware mechanisms are designed to achieve fine-grained spatio-temporally diverse approximation. Next, SHASTA proposes a Hardware-cognizant Approximation Tuning mechanism to tune an application's approximation to achieve the optimum execution efficiency under the prescribed error tolerance. The tuning mechanism is implemented atop a gradient descent algorithm and, thus, the application's approximation is tuned along the steepest error vs. execution efficiency gradient. Finally, SHASTA is designed with a full-system perspective, which achieves Synergic benefits across its optimizations, building a closer-to-ideal general purpose approximation system. SHASTA is implemented on top of an OOO core and achieves mean speedups/energy savings of 20%-40% over a non-approximate baseline for greater than 90% accuracy-these benefits are substantial for applications executing on a traditional general purpose processing system. SHASTA can be tuned to specific accuracy constraints and execution metrics and is quantitatively shown to achieve 2-15× higher benefits, in terms of performance and energy, compared to prior work.

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Section: Hw-cognizant Approximation Tuningmentioning

confidence: 99%

Section: Design Of Approximation Hardware 41 Compute Timing Approximmentioning

confidence: 99%

Section: Approximation At the Application Level Approximation Proposmentioning

confidence: 99%

mentioning

confidence: 99%

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Shasta

Ravi

Miguel

Lipasti

2020

ACM Trans. Archit. Code Optim.

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Power–Area-Optimized Approximate Multiplier Design for Image Fusion

Thakur,

Sohal,

Jain

2023

Circuits Syst Signal Process

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Low Error Efficient Approximate Adders for FPGAs

2021

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In this paper, we propose a methodology for designing low error efficient approximate adders for FPGAs. The proposed methodology utilizes FPGA resources efficiently to reduce the error of approximate adders. We propose two approximate adders for FPGAs using our methodology: low error and area efficient approximate adder (LEADx), and area and power efficient approximate adder (APEx). Both approximate adders are composed of an accurate and an approximate part. The approximate parts of these adders are designed in a systematic way to minimize the mean square error (MSE). LEADx has lower MSE than the approximate adders in the literature. The 32-bit LEADx with 16-bit approximation has 20% lower MSE than the approximate adder with the lowest MSE in the literature. The 16-bit APEx with 8-bit approximation has the same area, 60% lower MSE, and 4.5% less power consumption in Xilinx Virtex 7 FPGA than the smallest and lowest power consuming approximate adder in the literature. APEx has smaller area and lower power consumption than the other approximate adders in the literature. As a case study, the approximate adders are used in video encoding application. LEADx provided better quality than the other approximate adders for video encoding application. Therefore, our proposed approximate adders can be used for efficient FPGA implementations of error tolerant applications.

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Circuit Aware Approximate System Design With Case Studies in Image Processing and Neural Networks

Cited by 7 publications

References 25 publications

Shasta

Shasta

Power–Area-Optimized Approximate Multiplier Design for Image Fusion

Low Error Efficient Approximate Adders for FPGAs

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