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This project is funded by Flemish Agency for Innovation by Science and Technology (IWT) as SBO project OmniTrack.

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This paper presents a multicarrier 60GHz transmitter for distance measurement (ranging) in an indoor wireless localization system, achieving mm-precision with high update rate. The architecture comprises a baseband subcarrier generator, an upconverter, and a power amplifier. There are three key innovations, all stemming from careful hardware-algorithm co-design: 1. efficient frequency planning of the 6GHz-wide band; 2. power-efficient multicarrier signal generation by means of digital frequency divisions exploiting the phase-based time-of-arrival ranging algorithm; and 3. PAPR reduction to enable efficient operation of the power amplifier. By implementing these key techniques, 0.7-2.7mm precision is achieved over 5m measured distance with 5.4µs symbol duration. During operation, the core digital subcarrier generator generates 16 non-equidistant subcarriers from a 3GHz input clock, while consuming an average power of 1.8mW out of 0.9V supply. The upconverter and the power amplifier altogether consume around 127mW. The total area of the transmitter is 1.1mm2 . The chip is fabricated in a 40nm general purpose CMOS process.P. Indirayanti, T. Ayhan, M. Verhelst, W. Dehaene, and P. Reynaert are with the MICAS Division, Departement of Electrical Engineering (ESAT), KU Leuven,

This paper aims to exploit approximate computing units in image processing systems and artificial neural networks. For this purpose, a general design methodology is introduced, and approximationoriented architectures are developed for different applications. This paper proposes a method to compromise power/area efficiency of circuit-level design with accuracy supervision of system-level design. The proposed method selects approximate computational units that minimize the total computation cost, yet maintaining the ultimate performance. This is accomplished by formulating a linear programming problem, which can be solved by conventional linear programming solvers. Approximate computing units, such as multipliers, neurons, and convolution kernels, which are proposed by this paper, are suitable for power/area reduction through accuracy scaling. The formulation is demonstrated on applications in image processing, digital filters, and artificial neural networks. This way, the proposed technique and architectures are tested with different approximate computing units, as well as system-level requirement metrics, such as PSNR and classification performance. INDEX TERMS Approximate computing, artificial neural networks, field programmable gate arrays, high-level synthesis, image processing.