Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

“…The setup time requirement needs to be satisfied for the system to work correctly [1]. The setup time slack slack setup is defined as (12) where max(D 1,2 ) denotes the longest data transfer time from FF 1 to FF 2 . The setup time for FF 2 is t setup , specified in the cell library.…”

“…3) Effect of Phase-Shifting of the Supply Noise on Skitter: Several techniques, such as RC filtered buffers and "stacked" phase-shifted buffers [12], have been proposed to shift the φ seen by the clock paths. In 3-D clock distribution networks, these techniques can be applied to a part of the clock paths in a different tier to increase φ among tiers.…”

The combined effect of process variations and power supply noise on clock skew and jitter

“…The power supply noise v noise is modeled as a sinusoidal waveform with amplitude V n , frequency f n , and initial phase φ. This deterministic model is widely used to describe the first droop of the power supply noise, which is considered as the worst supply noise in a circuit [10], [12]. Other faster and more erratic droops of the supply noise can be included as random variables with probabilistic formulations, similar to process variations.…”

“…The (7) to (10) are obtained by the fitting expressions (12). The voltage noise v noise is determined through (4) and (5).…”

“…Simulation methods are used to obtain the delay variation of one buffer stage. The first droop of the power supply noise is investigated, since this first droop noise is, typically, the worst supply noise [10]- [12]. The proposed methodology can be integrated into the computeraided design flow of clock trees to design a robust clock distribution network.…”