The combined effect of process variations and power supply noise on clock skew and jitter

Abstract

Abstract-In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥ 110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤ 13%). The effect of widelyused techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise

“…Todri et al [6] has analyzed power supply noise and ground bounce for capturing worst-case path delay patterns based on simulated annealing. Xu [7] described a statistical model for skitter with PV and power supply noise effects. Peng [8] explains their work of pattern evaluation and selection considering crosstalk and PV.…”

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

“…In addition, the overhead of the adaptive circuits and architectural procedures can be reduced. A simplified model for skitter in 2-D ICs is proposed in [22], where only the uniform D2D variations and supply noise are considered.…”