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International audienceWith technology scaling, the growing impact of signal integrity issues imposes significant challenges in integrated circuit testing. They cause delay in the supply and ground networks, cross talk noise between multiple interconnects, variations in substrate and thermal noise parameters of the circuit, etc. Therefore, the consideration of signal integrity issues during pattern generation ensures a better path delay fault coverage. In this paper, we propose a constrained Automatic Test Pattern Generation(ATPG) flow to test path delay fault by simultaneously coupling multiple aggressors surrounding a delay sensitive victim path. This flow uses the most effective aggressors for pattern generation based on cross talk information predetermined from the layout of the circuit. We developed the constrained ATPG flow by customizing the existing scan-based techniques to generate functionally testable path delay faults. The proposed ATPG flow is applied to ITC'99 benchmark circuits. The comparison results with SPICE-based simulations shows the effectiveness of our pattern in determining worst-case path delay and also in terms of computation time

International audienceOngoing technology scaling has increased delay defects in integrated circuits. Some of the delay defects are due to crosstalk, supply noise, process variations, etc. They degrade the performance and field reliability of circuits. However, testing the circuits with path delay patterns under worst-case conditions helps to detect such defects. Estimation of patterns with worst-case path delay becomes difficult using the conventional techniques due to their unpredictable behavior. In this paper, we first describe the problem and then propose our approach in identifying a worst-case path delay pattern under the impact of process variations and supply noise. A delay probability metric ispresented in this work, for an efficient identification of worst-case path delay pattern, which is the basis of our ranking method. The simulation results of ITC'99 benchmark circuits show the feasibility of our delay probability metric.9-11 July 2014Tampa, F

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