Circuit design guidelines for n-channel MOSFET hot carrier robustness

Mistry, K.; Fox, T.F.; Preston, R.P.; Arora, N.D.; Doyle, B.S.; Nelsen, D.E.

doi:10.1109/16.216434

Cited by 45 publications

(7 citation statements)

References 44 publications

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“…7 A post-stress increase of interface traps was observed when holes were injected into the oxide. 5,6 Holes can be introduced into the oxide during irradiation 8,9 or by uniform 6,10 and nonuniform 5,11,12 electrical stress along the channel. Interface trap generation post-irradiation has been extensively studied and has been explained by a hydrogen transportation model.…”

Section: Introductionmentioning

confidence: 99%

Continuing degradation of the SiO2/Si interface after hot hole stress

Al-Kofahi

Zhang

Groeseneken

1997

Journal of Applied Physics

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This article reports new experimental results on the continuing interface trap generation post-hot hole injection and investigates the generation mechanism. The generation post-hole injection is found to be two orders of magnitude slower than that post-irradiation and cannot be satisfactorily explained by the transportation of hydrogen species across the gate oxide. The role played by the recombination of trapped holes with free electrons is examined. There is a lack of correlation between the trapped hole removal and the interface trap creation, which is against the prediction of the trapped hole conversion model. The results indicate that the interface traps generated during and post-stress originate from two different defects. The defect responsible for post-stress generation is excited by hole injection and then converted into an interface trap if a positive gate bias is applied. It is found that generation in a poly-Si gated metal-oxide-semiconductor field effect transistor behaves differently from that in an Al-gated device. The possible causes for this difference are discussed.

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Section: Introductionmentioning

confidence: 99%

Continuing degradation of the SiO2/Si interface after hot hole stress

Al-Kofahi

Zhang

Groeseneken

1997

Journal of Applied Physics

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“…While nitrided oxides can show maximum damage at high simultaneous drain and gate voltages (e.g., [9]), the conditions here were chosen as they are most representative of lifetime prediction under working circuit-operation conditions [11], [14], and 0741-3106/97$10.00 © 1997 IEEE thus of most interest for real-life microprocessor applications. Fig.…”

Section: Resultsmentioning

confidence: 99%

Role of nitridation/reoxidation of NH₃-nitrided gate dielectrics on the hot-carrier resistance of CMOS transistors

Doyle

Philipossian

1997

IEEE Electron Device Lett.

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The effect of nitriding and reoxidizing conditions are examined on the hot-carrier (HC) properties of p-channel and n-channel transistors with reoxidized nitrided oxide gate dielectrics. Nitrogen was introduced into the gate dielectric by performing cyclical nitridation and reoxidation steps (one cycle versus four cycles of nit./reox.), keeping the same overall oxidation and nitridation times constant. It was found that there were considerable differences in hot-carrier hardness, of up to three orders of magnitude for p-channel transistors, but much less for n-channel devices. Nitrogen-content variations (a factor of 2) for these very similar conditions explain the n-channel hot-carrier results. In the case of the p-MOS transistors, it is suggested that changes in hydrogen concentration might be responsible for their hot-carrier behavior.

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“…At the device level, as mentioned in the previous section, much of the highly active work on NMOS hot-carriers [37]- [39], has turned to PMOS NBTI degradation. Unlike hot-carrier degradation, NBTI degradation also exhibits a degradation recovery effect which has been extensively studied and modeled.…”

Section: New Technologiesmentioning

confidence: 98%

Compact modeling for simulation of circuit reliability: Historical and industrial perspectives

Lee¹

2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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This paper provides a historical background of the first developments of compact modeling for circuit-level reliability simulation at UC Berkeley, and the subsequent implementation into the BERT reliability simulator more than 20 years ago. A brief description of the advancement in the technology since then is given, and some industrial perspectives are summarized concerning how such a tool can be used to effectively optimize product design while ensuring reliability, as well as clarifying issues which still remain in the industrial design environment.

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Circuit design guidelines for n-channel MOSFET hot carrier robustness

Cited by 45 publications

References 44 publications

Continuing degradation of the SiO2/Si interface after hot hole stress

Continuing degradation of the SiO2/Si interface after hot hole stress

Role of nitridation/reoxidation of NH₃-nitrided gate dielectrics on the hot-carrier resistance of CMOS transistors

Compact modeling for simulation of circuit reliability: Historical and industrial perspectives

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Circuit design guidelines for n-channel MOSFET hot carrier robustness

Cited by 45 publications

References 44 publications

Continuing degradation of the SiO2/Si interface after hot hole stress

Continuing degradation of the SiO2/Si interface after hot hole stress

Role of nitridation/reoxidation of NH3-nitrided gate dielectrics on the hot-carrier resistance of CMOS transistors

Compact modeling for simulation of circuit reliability: Historical and industrial perspectives

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Role of nitridation/reoxidation of NH₃-nitrided gate dielectrics on the hot-carrier resistance of CMOS transistors